MUX 채널 수정
ch0: A0 ch1: A1 ch2: A2 ch3: A3 ch4: B3 ch5: B2
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@@ -101,22 +101,22 @@
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#define HALF_PERIOD_TICKS 4 /* half period: 250 ns / 62.5 ns = 4 ticks */
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/*==============================================================================
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* Piezo operating frequency
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* SW burst port register bitmasks
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*
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* Target: 2.1 MHz (HW burst mode).
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* SW burst timing is hard-coded per-frequency via NOP count.
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*
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* NOP timing (CPU 64 MHz, 1 NOP = 15.625 ns):
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* 1.7 MHz: half 294 ns -> 1st half 18 NOP, 2nd half 10 NOP + loop overhead
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* 1.8 MHz: half 278 ns -> 1st half 17 NOP, 2nd half 11 NOP + loop overhead
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* 1.9 MHz: half 263 ns -> 1st half 15 NOP, 2nd half 9 NOP + loop overhead
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* 2.0 MHz: half 250 ns -> 1st half 15 NOP, 2nd half 10 NOP + loop overhead
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* 2.1 MHz: half 238 ns -> 1st half 14 NOP, 2nd half 9 NOP + loop overhead
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* 2.2 MHz: half 227 ns -> 1st half 13 NOP, 2nd half 8 NOP + loop overhead
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*
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* To change frequency, modify NOP count in dr_piezo_burst_sw_XXmhz().
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* Pre-calculated from pin definitions in dr_piezo.h.
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* Used for direct writes to NRF_P1->OUT, enabling simultaneous multi-pin control.
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* PE is on P0 port, controlled separately via OUTSET/OUTCLR.
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*============================================================================*/
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#define PIEZO_FREQ_MHZ 2.1f /* default operating frequency (MHz) */
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/* Extract bit position within port from pin number (lower 5 bits = 0~31) */
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#define PIN_NUM(pin) ((pin) & 0x1F)
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#define P_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_P_OUT)) /* P1.07 positive output */
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#define N_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_N_OUT)) /* P1.06 negative output */
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#define PE_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_PE)) /* P0.25 pulse enable */
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#define DMP_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_DMP)) /* P1.00 dump control */
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/* Combined mask of piezo control pins on P1 port (excludes channel select pins) */
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#define P1_CTRL_MASK (P_OUT_MASK | N_OUT_MASK | DMP_MASK)
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/*==============================================================================
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* Static variables
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@@ -592,37 +592,37 @@ void dr_piezo_select_channel(uint8_t channel)
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{
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channel = channel & 0x07; /* Mask to 0~7 range */
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switch (channel) {
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// EN_A EN_B SEL0 SEL1
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case 0: // A0: 1 0 0 0
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switch (channel)
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{
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case 0: // A0: EN_MUXA=1, EN_MUXB=0, SEL0=0, SEL1=0
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
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nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
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break;
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case 1: // A2: 1 0 1 0
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case 1: // A1: EN_MUXA=1, EN_MUXB=0, SEL0=1, SEL1=0
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
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nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
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break;
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case 2: // A1: 1 0 0 1
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case 2: // A2: EN_MUXA=1, EN_MUXB=0, SEL0=0, SEL1=1
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
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nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
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break;
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case 3: // A3: 1 0 1 1
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case 3: // A3: EN_MUXA=1, EN_MUXB=0, SEL0=1, SEL1=1
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
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nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
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break;
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case 4: // B0: 0 1 1 1
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/*case 4: // B0: EN_MUXA=0, EN_MUXB=1, SEL0=1, SEL1=1
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
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nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
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break;
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case 5: // B1: 0 1 1 0
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case 5: // B1: EN_MUXA=0, EN_MUXB=1, SEL0=0, SEL1=1
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
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nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
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break;
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case 6: // B2: 0 1 0 1
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break;*/
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case 5: // B2: EN_MUXA=0, EN_MUXB=1, SEL0=1, SEL1=0
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
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nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
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break;
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case 7: // B3: 0 1 0 0
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case 4: // B3: EN_MUXA=0, EN_MUXB=1, SEL0=0, SEL1=0
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nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
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nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
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break;
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@@ -741,29 +741,6 @@ void dr_piezo_transmit(uint8_t cycles)
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* channel select pins (MUX SEL) via P1_CTRL_MASK (only control pins change).
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* PE is on P0 port, so it is controlled separately via OUTSET/OUTCLR registers.
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*============================================================================*/
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/* Extract bit position within port from pin number (lower 5 bits = 0~31) */
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#define PIN_NUM(pin) ((pin) & 0x1F)
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/* P1 port pin bitmasks - auto-generated from pin definitions in dr_piezo.h
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*
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* WARNING: Never hardcode pin numbers!
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* Hardcoding may save a developer's time temporarily,
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* but it will also shorten that developer's lifespan.
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* - Charles KWON
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*
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* Each mask represents the bit position within the port register.
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* Used for direct writes to NRF_P1->OUT, enabling simultaneous multi-pin control.
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*/
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#define P_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_P_OUT)) /* P1.07 positive output */
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#define N_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_N_OUT)) /* P1.06 negative output */
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#define PE_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_PE)) /* P0.25 pulse enable */
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#define DMP_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_DMP)) /* P1.00 dump control */
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/* Combined mask of piezo control pins on P1 port (excludes channel select pins) */
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#define P1_CTRL_MASK (P_OUT_MASK | N_OUT_MASK | DMP_MASK)
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/*
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* Software burst - default frequency 2.1MHz
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*
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