jh.chun/VesiScan-Basic-firmware-test
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ch0: A0
ch1: A1
ch2: A2
ch3: A3
ch4: B3
ch5: B2
This commit is contained in:
jhchun
2026-04-20 09:19:10 +09:00
parent 231a000849
commit 2db6e36c08
1 changed files with 25 additions and 48 deletions
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73
project/ble_peripheral/ble_app_bladder_patch/measurement/piezo/dr_piezo.c
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@@ -101,22 +101,22 @@
#define HALF_PERIOD_TICKS 4 /* half period: 250 ns / 62.5 ns = 4 ticks */ #define HALF_PERIOD_TICKS 4 /* half period: 250 ns / 62.5 ns = 4 ticks */
/*============================================================================== /*==============================================================================
* Piezo operating frequency * SW burst port register bitmasks
* *
* Target: 2.1 MHz (HW burst mode). * Pre-calculated from pin definitions in dr_piezo.h.
* SW burst timing is hard-coded per-frequency via NOP count. * Used for direct writes to NRF_P1->OUT, enabling simultaneous multi-pin control.
* * PE is on P0 port, controlled separately via OUTSET/OUTCLR.
* NOP timing (CPU 64 MHz, 1 NOP = 15.625 ns):
* 1.7 MHz: half 294 ns -> 1st half 18 NOP, 2nd half 10 NOP + loop overhead
* 1.8 MHz: half 278 ns -> 1st half 17 NOP, 2nd half 11 NOP + loop overhead
* 1.9 MHz: half 263 ns -> 1st half 15 NOP, 2nd half 9 NOP + loop overhead
* 2.0 MHz: half 250 ns -> 1st half 15 NOP, 2nd half 10 NOP + loop overhead
* 2.1 MHz: half 238 ns -> 1st half 14 NOP, 2nd half 9 NOP + loop overhead
* 2.2 MHz: half 227 ns -> 1st half 13 NOP, 2nd half 8 NOP + loop overhead
*
* To change frequency, modify NOP count in dr_piezo_burst_sw_XXmhz().
*============================================================================*/ *============================================================================*/
#define PIEZO_FREQ_MHZ 2.1f /* default operating frequency (MHz) */ /* Extract bit position within port from pin number (lower 5 bits = 0~31) */
#define PIN_NUM(pin) ((pin) & 0x1F)
#define P_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_P_OUT)) /* P1.07 positive output */
#define N_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_N_OUT)) /* P1.06 negative output */
#define PE_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_PE)) /* P0.25 pulse enable */
#define DMP_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_DMP)) /* P1.00 dump control */
/* Combined mask of piezo control pins on P1 port (excludes channel select pins) */
#define P1_CTRL_MASK (P_OUT_MASK | N_OUT_MASK | DMP_MASK)
/*============================================================================== /*==============================================================================
* Static variables * Static variables
@@ -592,37 +592,37 @@ void dr_piezo_select_channel(uint8_t channel)
{ {
channel = channel & 0x07; /* Mask to 0~7 range */ channel = channel & 0x07; /* Mask to 0~7 range */
switch (channel) { switch (channel)
// EN_A EN_B SEL0 SEL1 {
case 0: // A0: 1 0 0 0 case 0: // A0: EN_MUXA=1, EN_MUXB=0, SEL0=0, SEL1=0
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
break; break;
case 1: // A2: 1 0 1 0 case 1: // A1: EN_MUXA=1, EN_MUXB=0, SEL0=1, SEL1=0
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
break; break;
case 2: // A1: 1 0 0 1 case 2: // A2: EN_MUXA=1, EN_MUXB=0, SEL0=0, SEL1=1
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
break; break;
case 3: // A3: 1 0 1 1 case 3: // A3: EN_MUXA=1, EN_MUXB=0, SEL0=1, SEL1=1
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
break; break;
case 4: // B0: 0 1 1 1 /*case 4: // B0: EN_MUXA=0, EN_MUXB=1, SEL0=1, SEL1=1
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
break; break;
case 5: // B1: 0 1 1 0 case 5: // B1: EN_MUXA=0, EN_MUXB=1, SEL0=0, SEL1=1
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
break; break;*/
case 6: // B2: 0 1 0 1 case 5: // B2: EN_MUXA=0, EN_MUXB=1, SEL0=1, SEL1=0
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
break; break;
case 7: // B3: 0 1 0 0 case 4: // B3: EN_MUXA=0, EN_MUXB=1, SEL0=0, SEL1=0
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB); nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
break; break;
@@ -741,29 +741,6 @@ void dr_piezo_transmit(uint8_t cycles)
* channel select pins (MUX SEL) via P1_CTRL_MASK (only control pins change). * channel select pins (MUX SEL) via P1_CTRL_MASK (only control pins change).
* PE is on P0 port, so it is controlled separately via OUTSET/OUTCLR registers. * PE is on P0 port, so it is controlled separately via OUTSET/OUTCLR registers.
*============================================================================*/ *============================================================================*/
/* Extract bit position within port from pin number (lower 5 bits = 0~31) */
#define PIN_NUM(pin) ((pin) & 0x1F)
/* P1 port pin bitmasks - auto-generated from pin definitions in dr_piezo.h
*
* WARNING: Never hardcode pin numbers!
* Hardcoding may save a developer's time temporarily,
* but it will also shorten that developer's lifespan.
* - Charles KWON
*
* Each mask represents the bit position within the port register.
* Used for direct writes to NRF_P1->OUT, enabling simultaneous multi-pin control.
*/
#define P_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_P_OUT)) /* P1.07 positive output */
#define N_OUT_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_N_OUT)) /* P1.06 negative output */
#define PE_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_PE)) /* P0.25 pulse enable */
#define DMP_MASK (1UL << PIN_NUM(DR_PIEZO_PIN_DMP)) /* P1.00 dump control */
/* Combined mask of piezo control pins on P1 port (excludes channel select pins) */
#define P1_CTRL_MASK (P_OUT_MASK | N_OUT_MASK | DMP_MASK)
/* /*
* Software burst - default frequency 2.1MHz * Software burst - default frequency 2.1MHz
* *