Initial commit: MT firmware project
- BLE peripheral applications - dr_piezo and bladder_patch projects Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
This commit is contained in:
Charles Kwon
464
modules/nrfx/drivers/src/nrfx_qspi.c
Normal file
464
modules/nrfx/drivers/src/nrfx_qspi.c
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@@ -0,0 +1,464 @@
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/**
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* Copyright (c) 2016 - 2021, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
|
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* Semiconductor ASA integrated circuit in a product or a software update for
|
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
|
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <nrfx.h>
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#if NRFX_CHECK(NRFX_QSPI_ENABLED)
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#include <nrfx_qspi.h>
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#include <hal/nrf_gpio.h>
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/** @brief Command byte used to read status register. */
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#define QSPI_STD_CMD_RDSR 0x05
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/** @brief Byte used to mask status register and retrieve the write-in-progess bit. */
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#define QSPI_MEM_STATUSREG_WIP_Pos 0x01
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/** @brief Default time used in timeout function. */
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#define QSPI_DEF_WAIT_TIME_US 10
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/** @brief Default number of tries in timeout function. */
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#define QSPI_DEF_WAIT_ATTEMPTS 100
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/**
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* @brief Macro for initializing a QSPI pin.
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*
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* QSPI peripheral expects high drive pin strength.
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*/
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#define QSPI_PIN_INIT(_pin) nrf_gpio_cfg((_pin), \
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NRF_GPIO_PIN_DIR_INPUT, \
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NRF_GPIO_PIN_INPUT_DISCONNECT, \
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NRF_GPIO_PIN_NOPULL, \
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NRF_GPIO_PIN_H0H1, \
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NRF_GPIO_PIN_NOSENSE)
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/** @brief Control block - driver instance local data. */
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typedef struct
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{
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nrfx_qspi_handler_t handler; /**< Handler. */
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nrfx_drv_state_t state; /**< Driver state. */
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volatile bool is_busy; /**< Flag indicating that an operation is currently being performed. */
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void * p_context; /**< Driver context used in interrupt. */
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} qspi_control_block_t;
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static qspi_control_block_t m_cb;
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static nrfx_err_t qspi_task_perform(nrf_qspi_task_t task)
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{
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// Wait for peripheral
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if (m_cb.is_busy)
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{
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return NRFX_ERROR_BUSY;
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}
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nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
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if (m_cb.handler)
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{
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m_cb.is_busy = true;
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nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
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}
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nrf_qspi_task_trigger(NRF_QSPI, task);
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if (m_cb.handler == NULL)
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{
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while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
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{};
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}
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return NRFX_SUCCESS;
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}
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static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config)
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{
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// Check if the user set meaningful values to struct fields. If not, return false.
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if ((p_config->sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
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(p_config->csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
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(p_config->io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) ||
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(p_config->io1_pin == NRF_QSPI_PIN_NOT_CONNECTED))
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{
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return false;
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}
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QSPI_PIN_INIT(p_config->sck_pin);
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QSPI_PIN_INIT(p_config->csn_pin);
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QSPI_PIN_INIT(p_config->io0_pin);
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QSPI_PIN_INIT(p_config->io1_pin);
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if (p_config->io2_pin != NRF_QSPI_PIN_NOT_CONNECTED)
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{
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QSPI_PIN_INIT(p_config->io2_pin);
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}
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if (p_config->io3_pin != NRF_QSPI_PIN_NOT_CONNECTED)
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{
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QSPI_PIN_INIT(p_config->io3_pin);
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}
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nrf_qspi_pins_set(NRF_QSPI, p_config);
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return true;
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}
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static void qspi_pins_deconfigure(void)
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{
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nrf_qspi_pins_t pins;
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nrf_qspi_pins_get(NRF_QSPI, &pins);
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nrf_gpio_cfg_default(pins.sck_pin);
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nrf_gpio_cfg_default(pins.csn_pin);
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nrf_gpio_cfg_default(pins.io0_pin);
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nrf_gpio_cfg_default(pins.io1_pin);
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if (pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED)
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{
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nrf_gpio_cfg_default(pins.io2_pin);
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}
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if (pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED)
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{
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nrf_gpio_cfg_default(pins.io3_pin);
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}
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}
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static nrfx_err_t qspi_ready_wait(void)
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{
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bool result;
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NRFX_WAIT_FOR(nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY),
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QSPI_DEF_WAIT_ATTEMPTS,
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QSPI_DEF_WAIT_TIME_US,
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result);
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if (!result)
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{
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return NRFX_ERROR_TIMEOUT;
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}
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return NRFX_SUCCESS;
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}
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nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config,
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nrfx_qspi_handler_t handler,
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void * p_context)
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{
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NRFX_ASSERT(p_config);
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if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
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{
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return NRFX_ERROR_INVALID_STATE;
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}
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if (!qspi_pins_configure(&p_config->pins))
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{
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return NRFX_ERROR_INVALID_PARAM;
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}
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nrf_qspi_xip_offset_set(NRF_QSPI, p_config->xip_offset);
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nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if);
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nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if);
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m_cb.is_busy = false;
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m_cb.handler = handler;
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m_cb.p_context = p_context;
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/* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate
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task event ready)*/
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nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
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if (handler)
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{
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NRFX_IRQ_PRIORITY_SET(QSPI_IRQn, p_config->irq_priority);
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NRFX_IRQ_ENABLE(QSPI_IRQn);
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}
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m_cb.state = NRFX_DRV_STATE_INITIALIZED;
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nrf_qspi_enable(NRF_QSPI);
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nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
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nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ACTIVATE);
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// Waiting for the peripheral to activate
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return qspi_ready_wait();
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}
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nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config,
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void const * p_tx_buffer,
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void * p_rx_buffer)
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{
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NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
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if (m_cb.is_busy)
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{
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return NRFX_ERROR_BUSY;
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}
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nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
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/* In some cases, only opcode should be sent. To prevent execution, set function code is
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* surrounded by an if.
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*/
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if (p_tx_buffer)
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{
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nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer);
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}
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nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
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nrf_qspi_cinstr_transfer_start(NRF_QSPI, p_config);
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if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
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{
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// This timeout should never occur when WIPWAIT is not active, since in this
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// case the QSPI peripheral should send the command immediately, without any
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// waiting for previous write to complete.
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NRFX_ASSERT(p_config->wipwait);
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return NRFX_ERROR_TIMEOUT;
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}
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nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
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if (p_rx_buffer)
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{
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nrf_qspi_cinstrdata_get(NRF_QSPI, p_config->length, p_rx_buffer);
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}
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return NRFX_SUCCESS;
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}
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nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode,
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nrf_qspi_cinstr_len_t length,
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void const * p_tx_buffer)
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{
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nrf_qspi_cinstr_conf_t config = NRFX_QSPI_DEFAULT_CINSTR(opcode, length);
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return nrfx_qspi_cinstr_xfer(&config, p_tx_buffer, NULL);
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}
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nrfx_err_t nrfx_qspi_lfm_start(nrf_qspi_cinstr_conf_t const * p_config)
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{
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NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
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NRFX_ASSERT(!(nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI)));
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NRFX_ASSERT(p_config->length == NRF_QSPI_CINSTR_LEN_1B);
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if (m_cb.is_busy)
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{
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return NRFX_ERROR_BUSY;
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}
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nrf_qspi_cinstr_long_transfer_start(NRF_QSPI, p_config);
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if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
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{
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/* In case of error, abort long frame mode */
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nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, NRF_QSPI_CINSTR_LEN_1B, true);
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return NRFX_ERROR_TIMEOUT;
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}
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m_cb.is_busy = true;
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return NRFX_SUCCESS;
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}
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nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer,
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void * p_rx_buffer,
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size_t transfer_length,
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bool finalize)
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{
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NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
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NRFX_ASSERT(nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI));
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nrfx_err_t status = NRFX_SUCCESS;
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/* Perform transfers in packets of 8 bytes. Last transfer may be shorter. */
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nrf_qspi_cinstr_len_t length = NRF_QSPI_CINSTR_LEN_9B;
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for (uint32_t curr_byte = 0; curr_byte < transfer_length; curr_byte += 8)
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{
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uint32_t remaining_bytes = transfer_length - curr_byte;
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if (remaining_bytes < 8)
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{
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length = (nrf_qspi_cinstr_len_t)(remaining_bytes + 1);
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}
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if (p_tx_buffer)
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{
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nrf_qspi_cinstrdata_set(NRF_QSPI,
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length,
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&((uint8_t const *)p_tx_buffer)[curr_byte]);
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}
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nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
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if (remaining_bytes <= 8)
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{
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nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, length, finalize);
|
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}
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else
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{
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nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, length, false);
|
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}
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if (qspi_ready_wait() == NRFX_ERROR_TIMEOUT)
|
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{
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/* In case of error, abort long frame mode */
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nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, NRF_QSPI_CINSTR_LEN_1B, true);
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status = NRFX_ERROR_TIMEOUT;
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break;
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}
|
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|
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if (p_rx_buffer)
|
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{
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nrf_qspi_cinstrdata_get(NRF_QSPI,
|
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length,
|
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&((uint8_t *)p_rx_buffer)[curr_byte]);
|
||||
}
|
||||
}
|
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nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
|
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|
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if ((finalize) || (status == NRFX_ERROR_TIMEOUT))
|
||||
{
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m_cb.is_busy = false;
|
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}
|
||||
|
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return status;
|
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}
|
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|
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nrfx_err_t nrfx_qspi_mem_busy_check(void)
|
||||
{
|
||||
nrfx_err_t ret_code;
|
||||
uint8_t status_value = 0;
|
||||
|
||||
nrf_qspi_cinstr_conf_t const config =
|
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NRFX_QSPI_DEFAULT_CINSTR(QSPI_STD_CMD_RDSR,
|
||||
NRF_QSPI_CINSTR_LEN_2B);
|
||||
ret_code = nrfx_qspi_cinstr_xfer(&config, &status_value, &status_value);
|
||||
|
||||
if (ret_code != NRFX_SUCCESS)
|
||||
{
|
||||
return ret_code;
|
||||
}
|
||||
|
||||
if ((status_value & QSPI_MEM_STATUSREG_WIP_Pos) != 0x00)
|
||||
{
|
||||
return NRFX_ERROR_BUSY;
|
||||
}
|
||||
|
||||
return NRFX_SUCCESS;
|
||||
}
|
||||
|
||||
void nrfx_qspi_uninit(void)
|
||||
{
|
||||
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
|
||||
|
||||
if (nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI))
|
||||
{
|
||||
nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI, NRF_QSPI_CINSTR_LEN_1B, true);
|
||||
}
|
||||
|
||||
NRFX_IRQ_DISABLE(QSPI_IRQn);
|
||||
|
||||
nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);
|
||||
|
||||
nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_DEACTIVATE);
|
||||
|
||||
nrf_qspi_disable(NRF_QSPI);
|
||||
|
||||
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
|
||||
|
||||
qspi_pins_deconfigure();
|
||||
|
||||
m_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
|
||||
}
|
||||
|
||||
nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer,
|
||||
size_t tx_buffer_length,
|
||||
uint32_t dst_address)
|
||||
{
|
||||
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
|
||||
NRFX_ASSERT(p_tx_buffer != NULL);
|
||||
|
||||
if (!nrfx_is_in_ram(p_tx_buffer) || !nrfx_is_word_aligned(p_tx_buffer))
|
||||
{
|
||||
return NRFX_ERROR_INVALID_ADDR;
|
||||
}
|
||||
|
||||
nrf_qspi_write_buffer_set(NRF_QSPI, p_tx_buffer, tx_buffer_length, dst_address);
|
||||
return qspi_task_perform(NRF_QSPI_TASK_WRITESTART);
|
||||
}
|
||||
|
||||
nrfx_err_t nrfx_qspi_read(void * p_rx_buffer,
|
||||
size_t rx_buffer_length,
|
||||
uint32_t src_address)
|
||||
{
|
||||
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
|
||||
NRFX_ASSERT(p_rx_buffer != NULL);
|
||||
|
||||
if (!nrfx_is_in_ram(p_rx_buffer) || !nrfx_is_word_aligned(p_rx_buffer))
|
||||
{
|
||||
return NRFX_ERROR_INVALID_ADDR;
|
||||
}
|
||||
|
||||
nrf_qspi_read_buffer_set(NRF_QSPI, p_rx_buffer, rx_buffer_length, src_address);
|
||||
return qspi_task_perform(NRF_QSPI_TASK_READSTART);
|
||||
}
|
||||
|
||||
nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length,
|
||||
uint32_t start_address)
|
||||
{
|
||||
NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED);
|
||||
|
||||
if (!nrfx_is_word_aligned((void const *)start_address))
|
||||
{
|
||||
return NRFX_ERROR_INVALID_ADDR;
|
||||
}
|
||||
|
||||
nrf_qspi_erase_ptr_set(NRF_QSPI, start_address, length);
|
||||
return qspi_task_perform(NRF_QSPI_TASK_ERASESTART);
|
||||
}
|
||||
|
||||
nrfx_err_t nrfx_qspi_chip_erase(void)
|
||||
{
|
||||
return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0);
|
||||
}
|
||||
|
||||
void nrfx_qspi_irq_handler(void)
|
||||
{
|
||||
// Catch Event ready interrupts
|
||||
if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY))
|
||||
{
|
||||
m_cb.is_busy = false;
|
||||
nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY);
|
||||
m_cb.handler(NRFX_QSPI_EVENT_DONE, m_cb.p_context);
|
||||
}
|
||||
}
|
||||
|
||||
#endif // NRFX_CHECK(NRFX_QSPI_ENABLED)
|
||||
Reference in New Issue
Block a user