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jhchun
2026-04-15 11:49:02 +09:00
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336
modules/nrfx/hal/nrf_adc.h
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/**
* Copyright (c) 2014 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_ADC_H_
#define NRF_ADC_H_
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_adc_hal ADC HAL
* @{
* @ingroup nrf_adc
* @brief Hardware access layer for managing the Analog-to-Digital Converter (ADC)
* peripheral.
*/
/** @brief ADC interrupts. */
typedef enum
{
NRF_ADC_INT_END_MASK = ADC_INTENSET_END_Msk, /**< ADC interrupt on END event. */
} nrf_adc_int_mask_t;
/** @brief Resolution of the analog-to-digital converter. */
typedef enum
{
NRF_ADC_CONFIG_RES_8BIT = ADC_CONFIG_RES_8bit, /**< 8-bit resolution. */
NRF_ADC_CONFIG_RES_9BIT = ADC_CONFIG_RES_9bit, /**< 9-bit resolution. */
NRF_ADC_CONFIG_RES_10BIT = ADC_CONFIG_RES_10bit, /**< 10-bit resolution. */
} nrf_adc_config_resolution_t;
/** @brief Scaling factor of the analog-to-digital conversion. */
typedef enum
{
NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE = ADC_CONFIG_INPSEL_AnalogInputNoPrescaling, /**< Full scale input. */
NRF_ADC_CONFIG_SCALING_INPUT_TWO_THIRDS = ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling, /**< 2/3 scale input. */
NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD = ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling, /**< 1/3 scale input. */
NRF_ADC_CONFIG_SCALING_SUPPLY_TWO_THIRDS = ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling, /**< 2/3 of supply. */
NRF_ADC_CONFIG_SCALING_SUPPLY_ONE_THIRD = ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling /**< 1/3 of supply. */
} nrf_adc_config_scaling_t;
/** @brief External reference selection of the analog-to-digital converter. */
typedef enum
{
NRF_ADC_CONFIG_EXTREFSEL_NONE = ADC_CONFIG_EXTREFSEL_None, /**< Analog reference inputs disabled. */
NRF_ADC_CONFIG_EXTREFSEL_AREF0 = ADC_CONFIG_EXTREFSEL_AnalogReference0, /**< AREF0 as analog reference. */
NRF_ADC_CONFIG_EXTREFSEL_AREF1 = ADC_CONFIG_EXTREFSEL_AnalogReference1 /**< AREF1 as analog reference. */
} nrf_adc_config_extref_t;
/** @brief Reference selection of the analog-to-digital converter. */
typedef enum
{
NRF_ADC_CONFIG_REF_VBG = ADC_CONFIG_REFSEL_VBG, /**< 1.2 V reference. */
NRF_ADC_CONFIG_REF_SUPPLY_ONE_HALF = ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling, /**< 1/2 of power supply. */
NRF_ADC_CONFIG_REF_SUPPLY_ONE_THIRD = ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling, /**< 1/3 of power supply. */
NRF_ADC_CONFIG_REF_EXT = ADC_CONFIG_REFSEL_External /**< External reference. See @ref nrf_adc_config_extref_t for further configuration. */
} nrf_adc_config_reference_t;
/** @brief Input selection of the analog-to-digital converter. */
typedef enum
{
NRF_ADC_CONFIG_INPUT_DISABLED = ADC_CONFIG_PSEL_Disabled, /**< No input selected. */
NRF_ADC_CONFIG_INPUT_0 = ADC_CONFIG_PSEL_AnalogInput0, /**< Input 0. */
NRF_ADC_CONFIG_INPUT_1 = ADC_CONFIG_PSEL_AnalogInput1, /**< Input 1. */
NRF_ADC_CONFIG_INPUT_2 = ADC_CONFIG_PSEL_AnalogInput2, /**< Input 2. */
NRF_ADC_CONFIG_INPUT_3 = ADC_CONFIG_PSEL_AnalogInput3, /**< Input 3. */
NRF_ADC_CONFIG_INPUT_4 = ADC_CONFIG_PSEL_AnalogInput4, /**< Input 4. */
NRF_ADC_CONFIG_INPUT_5 = ADC_CONFIG_PSEL_AnalogInput5, /**< Input 5. */
NRF_ADC_CONFIG_INPUT_6 = ADC_CONFIG_PSEL_AnalogInput6, /**< Input 6. */
NRF_ADC_CONFIG_INPUT_7 = ADC_CONFIG_PSEL_AnalogInput7, /**< Input 7. */
} nrf_adc_config_input_t;
/** @brief Analog-to-digital converter tasks. */
typedef enum
{
NRF_ADC_TASK_START = offsetof(NRF_ADC_Type, TASKS_START), /**< ADC start sampling task. */
NRF_ADC_TASK_STOP = offsetof(NRF_ADC_Type, TASKS_STOP) /**< ADC stop sampling task. */
} nrf_adc_task_t;
/** @brief Analog-to-digital converter events. */
typedef enum
{
NRF_ADC_EVENT_END = offsetof(NRF_ADC_Type, EVENTS_END) /**< End of a conversion event. */
} nrf_adc_event_t;
/** @brief Analog-to-digital converter configuration. */
typedef struct
{
nrf_adc_config_resolution_t resolution; /**< ADC resolution. */
nrf_adc_config_scaling_t scaling; /**< ADC scaling factor. */
nrf_adc_config_reference_t reference; /**< ADC reference. */
nrf_adc_config_input_t input; /**< ADC input selection. */
nrf_adc_config_extref_t extref; /**< ADC external reference selection. */
} nrf_adc_config_t;
/** @brief Analog-to-digital value type. */
typedef uint16_t nrf_adc_value_t;
/**
* @brief Function for activating the specified ADC task.
*
* @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task);
/**
* @brief Function for getting the address of an ADC task register.
*
* @param[in] task ADC task.
*
* @return Address of the specified ADC task.
*/
__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t task);
/**
* @brief Function for retrieving the state of an ADC event.
*
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event);
/**
* @brief Function for clearing an ADC event.
*
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event);
/**
* @brief Function for getting the address of the specified ADC event register.
*
* @param[in] adc_event ADC event.
*
* @return Address of the specified ADC event.
*/
__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event);
/**
* @brief Function for enabling the specified interrupts.
*
* @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_adc_int_enable(uint32_t mask);
/**
* @brief Function for disabling the specified interrupts.
*
* @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_adc_int_disable(uint32_t mask);
/**
* @brief Function for retrieving the state of the specified ADC interrupts.
*
* @param[in] mask Mask of interrupts to be checked.
*
* @retval true All specified interrupts are enabled.
* @retval false At least one of the given interrupts is not enabled.
*/
__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t mask);
/**
* @brief Function for checking whether the ADC is busy.
*
* This function checks whether the ADC converter is busy with a conversion.
*
* @retval true The ADC is busy.
* @retval false The ADC is not busy.
*/
__STATIC_INLINE bool nrf_adc_busy_check(void);
/** @brief Function for enabling the ADC. */
__STATIC_INLINE void nrf_adc_enable(void);
/** @brief Function for disabling the ADC. */
__STATIC_INLINE void nrf_adc_disable(void);
/**
* @brief Function for checking if the ADC is enabled.
*
* @retval true The ADC is enabled.
* @retval false The ADC is not enabled.
*/
__STATIC_INLINE bool nrf_adc_enable_check(void);
/**
* @brief Function for retrieving the ADC conversion result.
*
* This function retrieves and returns the last analog-to-digital conversion result.
*
* @return Last conversion result.
*/
__STATIC_INLINE nrf_adc_value_t nrf_adc_result_get(void);
/**
* @brief Function for initializing the ADC.
*
* This function writes data to ADC's CONFIG register. After the configuration,
* the ADC is in DISABLE state and must be enabled before using it.
*
* @param[in] p_config Configuration parameters.
*/
__STATIC_INLINE void nrf_adc_init(nrf_adc_config_t const * p_config);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task)
{
*((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task)
{
return (uint32_t)((uint8_t *)NRF_ADC + (uint32_t)adc_task);
}
__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event);
}
__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event)
{
*((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event)
{
return (uint32_t)((uint8_t *)NRF_ADC + (uint32_t)adc_event);
}
__STATIC_INLINE void nrf_adc_int_enable(uint32_t mask)
{
NRF_ADC->INTENSET = mask;
}
__STATIC_INLINE void nrf_adc_int_disable(uint32_t mask)
{
NRF_ADC->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_adc_int_enable_check(uint32_t mask)
{
return (bool)(NRF_ADC->INTENSET & mask);
}
__STATIC_INLINE bool nrf_adc_busy_check(void)
{
return ((NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) == (ADC_BUSY_BUSY_Busy << ADC_BUSY_BUSY_Pos));
}
__STATIC_INLINE void nrf_adc_enable(void)
{
NRF_ADC->ENABLE = (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_adc_disable(void)
{
NRF_ADC->ENABLE = (ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE bool nrf_adc_enable_check(void)
{
return (NRF_ADC->ENABLE == (ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos));
}
__STATIC_INLINE nrf_adc_value_t nrf_adc_result_get(void)
{
return (nrf_adc_value_t)NRF_ADC->RESULT;
}
__STATIC_INLINE void nrf_adc_init(nrf_adc_config_t const * p_config)
{
NRF_ADC->CONFIG =
((p_config->resolution << ADC_CONFIG_RES_Pos) & ADC_CONFIG_RES_Msk)
|((p_config->scaling << ADC_CONFIG_INPSEL_Pos) & ADC_CONFIG_INPSEL_Msk)
|((p_config->reference << ADC_CONFIG_REFSEL_Pos) & ADC_CONFIG_REFSEL_Msk)
|((p_config->input << ADC_CONFIG_PSEL_Pos) & ADC_CONFIG_PSEL_Msk)
|((p_config->extref << ADC_CONFIG_EXTREFSEL_Pos) & ADC_CONFIG_EXTREFSEL_Msk);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* NRF_ADC_H_ */

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modules/nrfx/hal/nrf_comp.h
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/**
* Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_COMP_H_
#define NRF_COMP_H_
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_comp_hal COMP HAL
* @{
* @ingroup nrf_comp
* @brief Hardware access layer (HAL) for managing the Comparator (COMP) peripheral.
*/
/** @brief COMP analog pin selection. */
typedef enum
{
NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */
NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */
NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */
NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */
#if defined (COMP_PSEL_PSEL_AnalogInput4) || defined (__NRFX_DOXYGEN__)
NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_AnalogInput5) || defined (__NRFX_DOXYGEN__)
NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_AnalogInput6) || defined (__NRFX_DOXYGEN__)
NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_AnalogInput7) || defined (__NRFX_DOXYGEN__)
NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_VddDiv2) || defined (__NRFX_DOXYGEN__)
NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_VddhDiv5) || defined (__NRFX_DOXYGEN__)
NRF_COMP_VDDH_DIV5 = COMP_PSEL_PSEL_VddhDiv5, /*!< VDDH/5 selected as analog input. */
#endif
} nrf_comp_input_t;
/** @brief COMP reference selection. */
typedef enum
{
NRF_COMP_REF_Int1V2 = COMP_REFSEL_REFSEL_Int1V2, /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V). */
NRF_COMP_REF_Int1V8 = COMP_REFSEL_REFSEL_Int1V8, /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V). */
NRF_COMP_REF_Int2V4 = COMP_REFSEL_REFSEL_Int2V4, /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V). */
NRF_COMP_REF_VDD = COMP_REFSEL_REFSEL_VDD, /*!< VREF = VDD. */
NRF_COMP_REF_ARef = COMP_REFSEL_REFSEL_ARef /*!< VREF = AREF (VDD >= VREF >= AREFMIN). */
} nrf_comp_ref_t;
/** @brief COMP external analog reference selection. */
typedef enum
{
NRF_COMP_EXT_REF_0 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference0, /*!< Use AIN0 as external analog reference. */
NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1, /*!< Use AIN1 as external analog reference. */
NRF_COMP_EXT_REF_2 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference2, /*!< Use AIN2 as external analog reference. */
NRF_COMP_EXT_REF_3 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference3, /*!< Use AIN3 as external analog reference. */
#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference4) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_4 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference4, /*!< Use AIN4 as external analog reference. */
#endif
#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference5) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_5 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference5, /*!< Use AIN5 as external analog reference. */
#endif
#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference6) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_6 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference6, /*!< Use AIN6 as external analog reference. */
#endif
#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference7) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_7 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 /*!< Use AIN7 as external analog reference. */
#endif
} nrf_comp_ext_ref_t;
/** @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP. */
typedef struct
{
uint8_t th_down; /*!< THDOWN value. */
uint8_t th_up; /*!< THUP value. */
} nrf_comp_th_t;
/** @brief COMP main operation mode. */
typedef enum
{
NRF_COMP_MAIN_MODE_SE = COMP_MODE_MAIN_SE, /*!< Single-ended mode. */
NRF_COMP_MAIN_MODE_Diff = COMP_MODE_MAIN_Diff /*!< Differential mode. */
} nrf_comp_main_mode_t;
/** @brief COMP speed and power mode. */
typedef enum
{
NRF_COMP_SP_MODE_Low = COMP_MODE_SP_Low, /*!< Low power mode. */
NRF_COMP_SP_MODE_Normal = COMP_MODE_SP_Normal, /*!< Normal mode. */
NRF_COMP_SP_MODE_High = COMP_MODE_SP_High /*!< High-speed mode. */
} nrf_comp_sp_mode_t;
/** @brief COMP comparator hysteresis. */
typedef enum
{
NRF_COMP_HYST_NoHyst = COMP_HYST_HYST_NoHyst, /*!< Comparator hysteresis disabled. */
NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */
} nrf_comp_hyst_t;
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
/** @brief COMP current source selection on analog input. */
typedef enum
{
NRF_COMP_ISOURCE_Off = COMP_ISOURCE_ISOURCE_Off, /*!< Current source disabled. */
NRF_COMP_ISOURCE_Ien2uA5 = COMP_ISOURCE_ISOURCE_Ien2mA5, /*!< Current source enabled (+/- 2.5 uA). */
NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */
NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */
} nrf_isource_t;
#endif
/** @brief COMP tasks. */
typedef enum
{
NRF_COMP_TASK_START = offsetof(NRF_COMP_Type, TASKS_START), /*!< COMP start sampling task. */
NRF_COMP_TASK_STOP = offsetof(NRF_COMP_Type, TASKS_STOP), /*!< COMP stop sampling task. */
NRF_COMP_TASK_SAMPLE = offsetof(NRF_COMP_Type, TASKS_SAMPLE) /*!< Sample comparator value. */
} nrf_comp_task_t;
/** @brief COMP events. */
typedef enum
{
NRF_COMP_EVENT_READY = offsetof(NRF_COMP_Type, EVENTS_READY), /*!< COMP is ready and output is valid. */
NRF_COMP_EVENT_DOWN = offsetof(NRF_COMP_Type, EVENTS_DOWN), /*!< Input voltage crossed the threshold going down. */
NRF_COMP_EVENT_UP = offsetof(NRF_COMP_Type, EVENTS_UP), /*!< Input voltage crossed the threshold going up. */
NRF_COMP_EVENT_CROSS = offsetof(NRF_COMP_Type, EVENTS_CROSS) /*!< Input voltage crossed the threshold in any direction. */
} nrf_comp_event_t;
/** @brief COMP reference configuration. */
typedef struct
{
nrf_comp_ref_t reference; /*!< COMP reference selection. */
nrf_comp_ext_ref_t external; /*!< COMP external analog reference selection. */
} nrf_comp_ref_conf_t;
/** @brief Function for enabling the COMP peripheral. */
__STATIC_INLINE void nrf_comp_enable(void);
/** @brief Function for disabling the COMP peripheral. */
__STATIC_INLINE void nrf_comp_disable(void);
/**
* @brief Function for checking if the COMP peripheral is enabled.
*
* @retval true The COMP peripheral is enabled.
* @retval false The COMP peripheral is not enabled.
*/
__STATIC_INLINE bool nrf_comp_enable_check(void);
/**
* @brief Function for setting the reference source.
*
* @param[in] reference COMP reference selection.
*/
__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference);
/**
* @brief Function for setting the external analog reference source.
*
* @param[in] ext_ref COMP external analog reference selection.
*/
__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref);
/**
* @brief Function for setting threshold voltages.
*
* @param[in] threshold COMP VDOWN and VUP thresholds.
*/
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold);
/**
* @brief Function for setting the main mode.
*
* @param[in] main_mode COMP main operation mode.
*/
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode);
/**
* @brief Function for setting the speed mode.
*
* @param[in] speed_mode COMP speed and power mode.
*/
__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode);
/**
* @brief Function for setting the hysteresis.
*
* @param[in] hyst COMP comparator hysteresis.
*/
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst);
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
/**
* @brief Function for setting the current source on the analog input.
*
* @param[in] isource COMP current source selection on analog input.
*/
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource);
#endif
/**
* @brief Function for selecting the active input of the COMP.
*
* @param[in] input Input to be selected.
*/
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input);
/**
* @brief Function for getting the last COMP compare result.
*
* @note If VIN+ == VIN-, the return value depends on the previous result.
*
* @return The last compare result. If 0, then VIN+ < VIN-. If 1, then VIN+ > VIN-.
*/
__STATIC_INLINE uint32_t nrf_comp_result_get(void);
/**
* @brief Function for enabling interrupts from COMP.
*
* @param[in] mask Mask of interrupts to be enabled.
*
* @sa nrf_comp_int_enable_check
*/
__STATIC_INLINE void nrf_comp_int_enable(uint32_t mask);
/**
* @brief Function for disabling interrupts from COMP.
*
* @param[in] mask Mask of interrupts to be disabled.
*
* @sa nrf_comp_int_enable_check
*/
__STATIC_INLINE void nrf_comp_int_disable(uint32_t mask);
/**
* @brief Function for getting the enabled interrupts of COMP.
*
* @param[in] mask Mask of interrupts to be checked.
*
* @retval true At least one interrupt from the specified mask is enabled.
* @retval false No interrupt provided by the specified mask are enabled.
*/
__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t mask);
/**
* @brief Function for getting the address of the specified COMP task register.
*
* @param[in] task COMP task.
*
* @return Address of the specified COMP task.
*/
__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t task);
/**
* @brief Function for getting the address of the specified COMP event register.
*
* @param[in] event COMP event.
*
* @return Address of the specified COMP event.
*/
__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t event);
/**
* @brief Function for setting COMP shortcuts.
*
* @param[in] mask Mask of shortcuts.
*/
__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t mask);
/**
* @brief Function for clearing COMP shortcuts by mask.
*
* @param[in] mask Mask of shortcuts.
*/
__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t mask);
/**
* @brief Function for setting the specified COMP task.
*
* @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t task);
/**
* @brief Function for clearing the specified COMP event.
*
* @param[in] event COMP event to be cleared.
*/
__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t event);
/**
* @brief Function for retrieving the state of the UARTE event.
*
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t event);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_comp_enable(void)
{
NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Enabled << COMP_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_comp_disable(void)
{
NRF_COMP->ENABLE = (COMP_ENABLE_ENABLE_Disabled << COMP_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE bool nrf_comp_enable_check(void)
{
return ((NRF_COMP->ENABLE) & COMP_ENABLE_ENABLE_Enabled);
}
__STATIC_INLINE void nrf_comp_ref_set(nrf_comp_ref_t reference)
{
NRF_COMP->REFSEL = (reference << COMP_REFSEL_REFSEL_Pos);
}
__STATIC_INLINE void nrf_comp_ext_ref_set(nrf_comp_ext_ref_t ext_ref)
{
NRF_COMP->EXTREFSEL = (ext_ref << COMP_EXTREFSEL_EXTREFSEL_Pos);
}
__STATIC_INLINE void nrf_comp_th_set(nrf_comp_th_t threshold)
{
NRF_COMP->TH =
(((uint32_t)threshold.th_down << COMP_TH_THDOWN_Pos) & COMP_TH_THDOWN_Msk) |
(((uint32_t)threshold.th_up << COMP_TH_THUP_Pos) & COMP_TH_THUP_Msk);
}
__STATIC_INLINE void nrf_comp_main_mode_set(nrf_comp_main_mode_t main_mode)
{
NRF_COMP->MODE |= (main_mode << COMP_MODE_MAIN_Pos);
}
__STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode)
{
NRF_COMP->MODE |= (speed_mode << COMP_MODE_SP_Pos);
}
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst)
{
NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk;
}
#if defined (COMP_ISOURCE_ISOURCE_Msk)
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource)
{
NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk;
}
#endif
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input)
{
NRF_COMP->PSEL = ((uint32_t)input << COMP_PSEL_PSEL_Pos);
}
__STATIC_INLINE uint32_t nrf_comp_result_get(void)
{
return (uint32_t)NRF_COMP->RESULT;
}
__STATIC_INLINE void nrf_comp_int_enable(uint32_t mask)
{
NRF_COMP->INTENSET = mask;
}
__STATIC_INLINE void nrf_comp_int_disable(uint32_t mask)
{
NRF_COMP->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_comp_int_enable_check(uint32_t mask)
{
return (NRF_COMP->INTENSET & mask); // When read, this register returns the value of INTEN.
}
__STATIC_INLINE uint32_t * nrf_comp_task_address_get(nrf_comp_task_t task)
{
return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)task);
}
__STATIC_INLINE uint32_t * nrf_comp_event_address_get(nrf_comp_event_t event)
{
return (uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)event);
}
__STATIC_INLINE void nrf_comp_shorts_enable(uint32_t mask)
{
NRF_COMP->SHORTS |= mask;
}
__STATIC_INLINE void nrf_comp_shorts_disable(uint32_t mask)
{
NRF_COMP->SHORTS &= ~mask;
}
__STATIC_INLINE void nrf_comp_task_trigger(nrf_comp_task_t task)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)task) ) = 1;
}
__STATIC_INLINE void nrf_comp_event_clear(nrf_comp_event_t event)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)event) ) = 0;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_COMP + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_comp_event_check(nrf_comp_event_t event)
{
return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_COMP + (uint32_t)event));
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_COMP_H_

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modules/nrfx/hal/nrf_dppi.h
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@@ -1,341 +0,0 @@
/**
* Copyright (c) 2018 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_DPPI_H__
#define NRF_DPPI_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_dppi_hal DPPI Controller HAL
* @{
* @ingroup nrf_dppi
* @brief Hardware access layer for managing the Distributed Programmable Peripheral
* Interconnect Controller (DPPIC).
*/
/** @brief DPPI channel groups. */
typedef enum
{
NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
} nrf_dppi_channel_group_t;
/** @brief DPPI tasks. */
typedef enum
{
NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. */
NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0. */
NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. */
NRF_DPPI_TASK_CHG1_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].DIS), /**< Disable channel group 1. */
NRF_DPPI_TASK_CHG2_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].EN), /**< Enable channel group 2. */
NRF_DPPI_TASK_CHG2_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].DIS), /**< Disable channel group 2. */
NRF_DPPI_TASK_CHG3_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].EN), /**< Enable channel group 3. */
NRF_DPPI_TASK_CHG3_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].DIS), /**< Disable channel group 3. */
NRF_DPPI_TASK_CHG4_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].EN), /**< Enable channel group 4. */
NRF_DPPI_TASK_CHG4_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].DIS), /**< Disable channel group 4. */
NRF_DPPI_TASK_CHG5_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].EN), /**< Enable channel group 5. */
NRF_DPPI_TASK_CHG5_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].DIS) /**< Disable channel group 5. */
} nrf_dppi_task_t;
/**
* @brief Function for activating a DPPI task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] dppi_task Task to be activated.
*/
__STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
/**
* @brief Function for getting the address of the specified DPPI task register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Requested task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
nrf_dppi_task_t task);
/**
* @brief Function for checking the state of a specific DPPI channel.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] channel Channel to be checked.
*
* @retval true The channel is enabled.
* @retval false The channel is not enabled.
*/
__STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
/**
* @brief Function for enabling multiple DPPI channels.
*
* The bits in @c mask value correspond to particular channels. It means that
* writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1 etc.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Channel mask.
*/
__STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling multiple DPPI channels.
*
* The bits in @c mask value correspond to particular channels. It means that
* writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1 etc.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Channel mask.
*/
__STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling all DPPI channels.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg);
/**
* @brief Function for setting the subscribe configuration for a given
* DPPI task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to set the configuration.
* @param[in] channel Channel through which to subscribe events.
*/
__STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
nrf_dppi_task_t task,
uint8_t channel);
/**
* @brief Function for clearing the subscribe configuration for a given
* DPPI task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to clear the configuration.
*/
__STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task);
/**
* @brief Function for including multiple DPPI channels in a channel group.
*
* @details This function adds all specified channels to the group.
* The bits in @p channel_mask value correspond to particular channels. It means that
* writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] channel_mask Channels to be included in the group.
* @param[in] channel_group Channel group.
*/
__STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
uint32_t channel_mask,
nrf_dppi_channel_group_t channel_group);
/**
* @brief Function for removing multiple DPPI channels from a channel group.
*
* @details This function removes all specified channels from the group.
* The bits in @c channel_mask value correspond to particular channels. It means that
* writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] channel_mask Channels to be removed from the group.
* @param[in] channel_group Channel group.
*/
__STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
uint32_t channel_mask,
nrf_dppi_channel_group_t channel_group);
/**
* @brief Function for removing all DPPI channels from a channel group.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] group Channel group.
*/
__STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
nrf_dppi_channel_group_t group);
/**
* @brief Function for enabling a channel group.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] group Channel group.
*/
__STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
nrf_dppi_channel_group_t group);
/**
* @brief Function for disabling a channel group.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] group Channel group.
*/
__STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
nrf_dppi_channel_group_t group);
/**
* @brief Function for getting the ENABLE task associated with the specified channel group.
*
* @param[in] index Channel group index.
*
* @return Requested ENABLE task.
*/
__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index);
/**
* @brief Function for getting the DISABLE task associated with the specified channel group.
*
* @param[in] index Channel group index.
*
* @return Requested DISABLE task.
*/
__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
}
__STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
nrf_dppi_task_t task)
{
return (uint32_t) ((uint8_t *) p_reg + (uint32_t ) task);
}
__STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
{
return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
}
__STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)
{
p_reg->CHENCLR = 0xFFFFFFFFuL;
}
__STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
{
p_reg->CHENSET = mask;
}
__STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
{
p_reg->CHENCLR = mask;
}
__STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
nrf_dppi_task_t task,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
}
__STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
}
__STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
uint32_t channel_mask,
nrf_dppi_channel_group_t channel_group)
{
p_reg->CHG[(uint32_t) channel_group] =
p_reg->CHG[(uint32_t) channel_group] | (channel_mask);
}
__STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
uint32_t channel_mask,
nrf_dppi_channel_group_t channel_group)
{
p_reg->CHG[(uint32_t) channel_group] =
p_reg->CHG[(uint32_t) channel_group] & ~(channel_mask);
}
__STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
nrf_dppi_channel_group_t group)
{
p_reg->CHG[(uint32_t) group] = 0;
}
__STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg, nrf_dppi_channel_group_t group)
{
p_reg->TASKS_CHG[(uint32_t) group].EN = 1;
}
__STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
nrf_dppi_channel_group_t group)
{
p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
}
__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index)
{
NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_DPPIC->TASKS_CHG));
return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].EN);
}
__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index)
{
NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_DPPIC->TASKS_CHG));
return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].DIS);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_DPPIC_H__

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@@ -1,621 +0,0 @@
/**
* Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_I2S_H__
#define NRF_I2S_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_i2s_hal I2S HAL
* @{
* @ingroup nrf_i2s
* @brief Hardware access layer for managing the Inter-IC Sound (I2S) peripheral.
*/
/**
* @brief This value can be provided as a parameter for the @ref nrf_i2s_pins_set
* function call to specify that the given I2S signal (SDOUT, SDIN, or MCK)
* shall not be connected to a physical pin.
*/
#define NRF_I2S_PIN_NOT_CONNECTED 0xFFFFFFFF
/** @brief I2S tasks. */
typedef enum
{
NRF_I2S_TASK_START = offsetof(NRF_I2S_Type, TASKS_START), ///< Starts continuous I2S transfer. Also starts the MCK generator if this is enabled.
NRF_I2S_TASK_STOP = offsetof(NRF_I2S_Type, TASKS_STOP) ///< Stops I2S transfer. Also stops the MCK generator.
} nrf_i2s_task_t;
/** @brief I2S events. */
typedef enum
{
NRF_I2S_EVENT_RXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_RXPTRUPD), ///< The RXD.PTR register has been copied to internal double buffers.
NRF_I2S_EVENT_TXPTRUPD = offsetof(NRF_I2S_Type, EVENTS_TXPTRUPD), ///< The TXD.PTR register has been copied to internal double buffers.
NRF_I2S_EVENT_STOPPED = offsetof(NRF_I2S_Type, EVENTS_STOPPED) ///< I2S transfer stopped.
} nrf_i2s_event_t;
/** @brief I2S interrupts. */
typedef enum
{
NRF_I2S_INT_RXPTRUPD_MASK = I2S_INTENSET_RXPTRUPD_Msk, ///< Interrupt on RXPTRUPD event.
NRF_I2S_INT_TXPTRUPD_MASK = I2S_INTENSET_TXPTRUPD_Msk, ///< Interrupt on TXPTRUPD event.
NRF_I2S_INT_STOPPED_MASK = I2S_INTENSET_STOPPED_Msk ///< Interrupt on STOPPED event.
} nrf_i2s_int_mask_t;
/** @brief I2S modes of operation. */
typedef enum
{
NRF_I2S_MODE_MASTER = I2S_CONFIG_MODE_MODE_Master, ///< Master mode.
NRF_I2S_MODE_SLAVE = I2S_CONFIG_MODE_MODE_Slave ///< Slave mode.
} nrf_i2s_mode_t;
/** @brief I2S master clock generator settings. */
typedef enum
{
NRF_I2S_MCK_DISABLED = 0, ///< MCK disabled.
#if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2) || defined(__NRFX_DOXYGEN__)
// [conversion to 'int' needed to prevent compilers from complaining
// that the provided value (0x80000000UL) is out of range of "int"]
NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz.
#endif
#if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3) || defined(__NRFX_DOXYGEN__)
NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz.
#endif
#if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4) || defined(__NRFX_DOXYGEN__)
NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz.
#endif
#if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5) || defined(__NRFX_DOXYGEN__)
NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz.
#endif
#if defined(I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6) || defined(__NRFX_DOXYGEN__)
NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz.
#endif
NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz.
NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz.
NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz.
NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz.
NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz.
NRF_I2S_MCK_32MDIV21 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21, ///< 32 MHz / 21 = 1.5238095 MHz.
NRF_I2S_MCK_32MDIV23 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23, ///< 32 MHz / 23 = 1.3913043 MHz.
NRF_I2S_MCK_32MDIV30 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30, ///< 32 MHz / 30 = 1.0666667 MHz.
NRF_I2S_MCK_32MDIV31 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31, ///< 32 MHz / 31 = 1.0322581 MHz.
NRF_I2S_MCK_32MDIV32 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32, ///< 32 MHz / 32 = 1.0 MHz.
NRF_I2S_MCK_32MDIV42 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42, ///< 32 MHz / 42 = 0.7619048 MHz.
NRF_I2S_MCK_32MDIV63 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63, ///< 32 MHz / 63 = 0.5079365 MHz.
NRF_I2S_MCK_32MDIV125 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 ///< 32 MHz / 125 = 0.256 MHz.
} nrf_i2s_mck_t;
/** @brief I2S MCK/LRCK ratios. */
typedef enum
{
NRF_I2S_RATIO_32X = I2S_CONFIG_RATIO_RATIO_32X, ///< LRCK = MCK / 32.
NRF_I2S_RATIO_48X = I2S_CONFIG_RATIO_RATIO_48X, ///< LRCK = MCK / 48.
NRF_I2S_RATIO_64X = I2S_CONFIG_RATIO_RATIO_64X, ///< LRCK = MCK / 64.
NRF_I2S_RATIO_96X = I2S_CONFIG_RATIO_RATIO_96X, ///< LRCK = MCK / 96.
NRF_I2S_RATIO_128X = I2S_CONFIG_RATIO_RATIO_128X, ///< LRCK = MCK / 128.
NRF_I2S_RATIO_192X = I2S_CONFIG_RATIO_RATIO_192X, ///< LRCK = MCK / 192.
NRF_I2S_RATIO_256X = I2S_CONFIG_RATIO_RATIO_256X, ///< LRCK = MCK / 256.
NRF_I2S_RATIO_384X = I2S_CONFIG_RATIO_RATIO_384X, ///< LRCK = MCK / 384.
NRF_I2S_RATIO_512X = I2S_CONFIG_RATIO_RATIO_512X ///< LRCK = MCK / 512.
} nrf_i2s_ratio_t;
/** @brief I2S sample widths. */
typedef enum
{
NRF_I2S_SWIDTH_8BIT = I2S_CONFIG_SWIDTH_SWIDTH_8Bit, ///< 8 bit.
NRF_I2S_SWIDTH_16BIT = I2S_CONFIG_SWIDTH_SWIDTH_16Bit, ///< 16 bit.
NRF_I2S_SWIDTH_24BIT = I2S_CONFIG_SWIDTH_SWIDTH_24Bit ///< 24 bit.
} nrf_i2s_swidth_t;
/** @brief I2S alignments of sample within a frame. */
typedef enum
{
NRF_I2S_ALIGN_LEFT = I2S_CONFIG_ALIGN_ALIGN_Left, ///< Left-aligned.
NRF_I2S_ALIGN_RIGHT = I2S_CONFIG_ALIGN_ALIGN_Right ///< Right-aligned.
} nrf_i2s_align_t;
/** @brief I2S frame formats. */
typedef enum
{
NRF_I2S_FORMAT_I2S = I2S_CONFIG_FORMAT_FORMAT_I2S, ///< Original I2S format.
NRF_I2S_FORMAT_ALIGNED = I2S_CONFIG_FORMAT_FORMAT_Aligned ///< Alternate (left-aligned or right-aligned) format.
} nrf_i2s_format_t;
/** @brief I2S enabled channels. */
typedef enum
{
NRF_I2S_CHANNELS_STEREO = I2S_CONFIG_CHANNELS_CHANNELS_Stereo, ///< Stereo.
NRF_I2S_CHANNELS_LEFT = I2S_CONFIG_CHANNELS_CHANNELS_Left, ///< Left only.
NRF_I2S_CHANNELS_RIGHT = I2S_CONFIG_CHANNELS_CHANNELS_Right ///< Right only.
} nrf_i2s_channels_t;
/**
* @brief Function for activating the specified I2S task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,
nrf_i2s_task_t task);
/**
* @brief Function for getting the address of the specified I2S task register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Specified task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,
nrf_i2s_task_t task);
/**
* @brief Function for clearing the specified I2S event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event);
/**
* @brief Function for retrieving the state of the I2S event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
nrf_i2s_event_t event);
/**
* @brief Function for getting the address of the specified I2S event register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Specified event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,
nrf_i2s_event_t event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] i2s_int Interrupt to be checked.
*
* @retval true The interrupt is enabled.
* @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg,
nrf_i2s_int_mask_t i2s_int);
/**
* @brief Function for enabling the I2S peripheral.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_reg);
/**
* @brief Function for disabling the I2S peripheral.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_reg);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting the subscribe configuration for a given
* I2S task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to set the configuration.
* @param[in] channel Channel through which to subscribe events.
*/
__STATIC_INLINE void nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,
nrf_i2s_task_t task,
uint8_t channel);
/**
* @brief Function for clearing the subscribe configuration for a given
* I2S task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to clear the configuration.
*/
__STATIC_INLINE void nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,
nrf_i2s_task_t task);
/**
* @brief Function for setting the publish configuration for a given
* I2S event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event for which to set the configuration.
* @param[in] channel Channel through which to publish the event.
*/
__STATIC_INLINE void nrf_i2s_publish_set(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event,
uint8_t channel);
/**
* @brief Function for clearing the publish configuration for a given
* I2S event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event for which to clear the configuration.
*/
__STATIC_INLINE void nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event);
#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for configuring I2S pins.
*
* Usage of the SDOUT, SDIN, and MCK signals is optional.
* If a given signal is not needed, pass the @ref NRF_I2S_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] sck_pin SCK pin number.
* @param[in] lrck_pin LRCK pin number.
* @param[in] mck_pin MCK pin number.
* @param[in] sdout_pin SDOUT pin number.
* @param[in] sdin_pin SDIN pin number.
*/
__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg,
uint32_t sck_pin,
uint32_t lrck_pin,
uint32_t mck_pin,
uint32_t sdout_pin,
uint32_t sdin_pin);
/**
* @brief Function for setting the I2S peripheral configuration.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mode Mode of operation (master or slave).
* @param[in] format I2S frame format.
* @param[in] alignment Alignment of sample within a frame.
* @param[in] sample_width Sample width.
* @param[in] channels Enabled channels.
* @param[in] mck_setup Master clock generator setup.
* @param[in] ratio MCK/LRCK ratio.
*
* @retval true The configuration has been set successfully.
* @retval false The specified configuration is not allowed.
*/
__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
nrf_i2s_mode_t mode,
nrf_i2s_format_t format,
nrf_i2s_align_t alignment,
nrf_i2s_swidth_t sample_width,
nrf_i2s_channels_t channels,
nrf_i2s_mck_t mck_setup,
nrf_i2s_ratio_t ratio);
/**
* @brief Function for setting up the I2S transfer.
*
* This function sets up the RX and TX buffers and enables reception or
* transmission (or both) accordingly. If the transfer in a given direction is not
* required, pass NULL instead of the pointer to the corresponding buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] size Size of the buffers (in 32-bit words).
* @param[in] p_rx_buffer Pointer to the receive buffer.
* Pass NULL to disable reception.
* @param[in] p_tx_buffer Pointer to the transmit buffer.
* Pass NULL to disable transmission.
*/
__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,
uint16_t size,
uint32_t * p_rx_buffer,
uint32_t const * p_tx_buffer);
/**
* @brief Function for setting the pointer to the receive buffer.
*
* @note The size of the buffer can be set only by calling
* @ref nrf_i2s_transfer_set.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the receive buffer.
*/
__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,
uint32_t * p_buffer);
/**
* @brief Function for getting the pointer to the receive buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Pointer to the receive buffer.
*/
__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg);
/**
* @brief Function for setting the pointer to the transmit buffer.
*
* @note The size of the buffer can be set only by calling
* @ref nrf_i2s_transfer_set.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the transmit buffer.
*/
__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,
uint32_t const * p_buffer);
/**
* @brief Function for getting the pointer to the transmit buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Pointer to the transmit buffer.
*/
__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_i2s_task_trigger(NRF_I2S_Type * p_reg,
nrf_i2s_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_i2s_task_address_get(NRF_I2S_Type const * p_reg,
nrf_i2s_task_t task)
{
return ((uint32_t)p_reg + (uint32_t)task);
}
__STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
nrf_i2s_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE uint32_t nrf_i2s_event_address_get(NRF_I2S_Type const * p_reg,
nrf_i2s_event_t event)
{
return ((uint32_t)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_i2s_int_enable(NRF_I2S_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_i2s_int_disable(NRF_I2S_Type * p_reg, uint32_t mask)
{
p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_i2s_int_enable_check(NRF_I2S_Type const * p_reg,
nrf_i2s_int_mask_t i2s_int)
{
return (bool)(p_reg->INTENSET & i2s_int);
}
__STATIC_INLINE void nrf_i2s_enable(NRF_I2S_Type * p_reg)
{
p_reg->ENABLE = (I2S_ENABLE_ENABLE_Enabled << I2S_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_i2s_disable(NRF_I2S_Type * p_reg)
{
p_reg->ENABLE = (I2S_ENABLE_ENABLE_Disabled << I2S_ENABLE_ENABLE_Pos);
}
#if defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_i2s_subscribe_set(NRF_I2S_Type * p_reg,
nrf_i2s_task_t task,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | I2S_SUBSCRIBE_START_EN_Msk);
}
__STATIC_INLINE void nrf_i2s_subscribe_clear(NRF_I2S_Type * p_reg,
nrf_i2s_task_t task)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
}
__STATIC_INLINE void nrf_i2s_publish_set(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
((uint32_t)channel | I2S_PUBLISH_STOPPED_EN_Msk);
}
__STATIC_INLINE void nrf_i2s_publish_clear(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
}
#endif // defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg,
uint32_t sck_pin,
uint32_t lrck_pin,
uint32_t mck_pin,
uint32_t sdout_pin,
uint32_t sdin_pin)
{
p_reg->PSEL.SCK = sck_pin;
p_reg->PSEL.LRCK = lrck_pin;
p_reg->PSEL.MCK = mck_pin;
p_reg->PSEL.SDOUT = sdout_pin;
p_reg->PSEL.SDIN = sdin_pin;
}
__STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
nrf_i2s_mode_t mode,
nrf_i2s_format_t format,
nrf_i2s_align_t alignment,
nrf_i2s_swidth_t sample_width,
nrf_i2s_channels_t channels,
nrf_i2s_mck_t mck_setup,
nrf_i2s_ratio_t ratio)
{
if (mode == NRF_I2S_MODE_MASTER)
{
// The MCK/LRCK ratio must be a multiple of 2 * sample width.
if (((sample_width == NRF_I2S_SWIDTH_16BIT) &&
(ratio == NRF_I2S_RATIO_48X))
||
((sample_width == NRF_I2S_SWIDTH_24BIT) &&
((ratio == NRF_I2S_RATIO_32X) ||
(ratio == NRF_I2S_RATIO_64X) ||
(ratio == NRF_I2S_RATIO_128X) ||
(ratio == NRF_I2S_RATIO_256X) ||
(ratio == NRF_I2S_RATIO_512X))))
{
return false;
}
}
p_reg->CONFIG.MODE = mode;
p_reg->CONFIG.FORMAT = format;
p_reg->CONFIG.ALIGN = alignment;
p_reg->CONFIG.SWIDTH = sample_width;
p_reg->CONFIG.CHANNELS = channels;
p_reg->CONFIG.RATIO = ratio;
if (mck_setup == NRF_I2S_MCK_DISABLED)
{
p_reg->CONFIG.MCKEN =
(I2S_CONFIG_MCKEN_MCKEN_Disabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
}
else
{
p_reg->CONFIG.MCKFREQ = mck_setup;
p_reg->CONFIG.MCKEN =
(I2S_CONFIG_MCKEN_MCKEN_Enabled << I2S_CONFIG_MCKEN_MCKEN_Pos);
}
return true;
}
__STATIC_INLINE void nrf_i2s_transfer_set(NRF_I2S_Type * p_reg,
uint16_t size,
uint32_t * p_buffer_rx,
uint32_t const * p_buffer_tx)
{
p_reg->RXTXD.MAXCNT = size;
nrf_i2s_rx_buffer_set(p_reg, p_buffer_rx);
p_reg->CONFIG.RXEN = (p_buffer_rx != NULL) ? 1 : 0;
nrf_i2s_tx_buffer_set(p_reg, p_buffer_tx);
p_reg->CONFIG.TXEN = (p_buffer_tx != NULL) ? 1 : 0;
}
__STATIC_INLINE void nrf_i2s_rx_buffer_set(NRF_I2S_Type * p_reg,
uint32_t * p_buffer)
{
p_reg->RXD.PTR = (uint32_t)p_buffer;
}
__STATIC_INLINE uint32_t * nrf_i2s_rx_buffer_get(NRF_I2S_Type const * p_reg)
{
return (uint32_t *)(p_reg->RXD.PTR);
}
__STATIC_INLINE void nrf_i2s_tx_buffer_set(NRF_I2S_Type * p_reg,
uint32_t const * p_buffer)
{
p_reg->TXD.PTR = (uint32_t)p_buffer;
}
__STATIC_INLINE uint32_t * nrf_i2s_tx_buffer_get(NRF_I2S_Type const * p_reg)
{
return (uint32_t *)(p_reg->TXD.PTR);
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_I2S_H__

411
modules/nrfx/hal/nrf_lpcomp.h
View File

@@ -1,411 +0,0 @@
/**
* Copyright (c) 2014 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_LPCOMP_H_
#define NRF_LPCOMP_H_
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_lpcomp_hal LPCOMP HAL
* @{
* @ingroup nrf_lpcomp
* @brief Hardware access layer for managing the Low Power Comparator (LPCOMP) peripheral.
*/
/** @brief LPCOMP reference selection. */
typedef enum
{
#if (LPCOMP_REFSEL_RESOLUTION == 8) || defined(__NRFX_DOXYGEN__)
NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling, /**< Use supply with a 1/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling, /**< Use supply with a 2/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, /**< Use supply with a 3/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling, /**< Use supply with a 4/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling, /**< Use supply with a 5/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, /**< Use supply with a 6/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, /**< Use supply with a 7/8 prescaler as reference. */
#elif (LPCOMP_REFSEL_RESOLUTION == 16) || defined(__NRFX_DOXYGEN__)
NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, /**< Use supply with a 1/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, /**< Use supply with a 2/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, /**< Use supply with a 3/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, /**< Use supply with a 4/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, /**< Use supply with a 5/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, /**< Use supply with a 6/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, /**< Use supply with a 7/8 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, /**< Use supply with a 1/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, /**< Use supply with a 3/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, /**< Use supply with a 5/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, /**< Use supply with a 7/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, /**< Use supply with a 9/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref11_16Vdd, /**< Use supply with a 11/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref13_16Vdd, /**< Use supply with a 13/16 prescaler as reference. */
NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref15_16Vdd, /**< Use supply with a 15/16 prescaler as reference. */
#endif
NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef |
(LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), /**< External reference 0. */
NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef |
(LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), /**< External reference 1. */
} nrf_lpcomp_ref_t;
/** @brief LPCOMP input selection. */
typedef enum
{
NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */
NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */
NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */
NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */
NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */
NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */
NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */
NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */
} nrf_lpcomp_input_t;
/** @brief LPCOMP detection type selection. */
typedef enum
{
NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */
NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, /**< Generate ANADETEC on upwards crossing only. */
NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */
} nrf_lpcomp_detect_t;
/** @brief LPCOMP tasks. */
typedef enum
{
NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */
NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */
NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */
} nrf_lpcomp_task_t;
/** @brief LPCOMP events. */
typedef enum
{
NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */
NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */
NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */
NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */
} nrf_lpcomp_event_t;
/** @brief LPCOMP shortcut masks. */
typedef enum
{
NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Shortcut between CROSS event and STOP task. */
NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Shortcut between UP event and STOP task. */
NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Shortcut between DOWN event and STOP task. */
NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Shortcut between READY event and STOP task. */
NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Shortcut between READY event and SAMPLE task. */
} nrf_lpcomp_short_mask_t;
#ifdef LPCOMP_FEATURE_HYST_PRESENT
/** @brief LPCOMP hysteresis. */
typedef enum
{
NRF_LPCOMP_HYST_NOHYST = LPCOMP_HYST_HYST_NoHyst, /**< Comparator hysteresis disabled. */
NRF_LPCOMP_HYST_50mV = LPCOMP_HYST_HYST_Hyst50mV /**< Comparator hysteresis enabled (typically 50 mV). */
}nrf_lpcomp_hysteresis_t;
#endif // LPCOMP_FEATURE_HYST_PRESENT
/** @brief LPCOMP configuration. */
typedef struct
{
nrf_lpcomp_ref_t reference; /**< LPCOMP reference. */
nrf_lpcomp_detect_t detection; /**< LPCOMP detection type. */
#ifdef LPCOMP_FEATURE_HYST_PRESENT
nrf_lpcomp_hysteresis_t hyst; /**< LPCOMP hysteresis. */
#endif // LPCOMP_FEATURE_HYST_PRESENT
} nrf_lpcomp_config_t;
/** Default LPCOMP configuration. */
#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN }
/**
* @brief Function for configuring LPCOMP.
*
* This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration,
* so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped.
*
* @param[in] p_config Configuration.
*/
__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config);
/**
* @brief Function for selecting the LPCOMP input.
*
* This function selects the active input of LPCOMP.
*
* @param[in] input Input to be selected.
*/
__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input);
/**
* @brief Function for enabling the Low Power Comparator.
*
* This function enables LPCOMP.
*/
__STATIC_INLINE void nrf_lpcomp_enable(void);
/**
* @brief Function for disabling the Low Power Comparator.
*
* This function disables LPCOMP.
*/
__STATIC_INLINE void nrf_lpcomp_disable(void);
/**
* @brief Function for getting the last LPCOMP compare result.
*
* @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite.
*/
__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void);
/**
* @brief Function for enabling interrupts from LPCOMP.
*
* @param[in] int_mask Mask of interrupts to be enabled.
*
* @sa nrf_lpcomp_int_disable
* @sa nrf_lpcomp_int_enable_check
*/
__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t int_mask);
/**
* @brief Function for disabling interrupts from LPCOMP.
*
* @param[in] int_mask Mask of interrupts to be disabled.
*
* @sa nrf_lpcomp_int_enable
* @sa nrf_lpcomp_int_enable_check
*/
__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t int_mask);
/**
* @brief Function for getting the enabled interrupts of LPCOMP.
*
* @param[in] int_mask Mask of interrupts to be checked.
*
* @retval true Any of interrupts of the specified mask are enabled.
* @retval false None interrupt specified by the mask are enabled.
*
* @sa nrf_lpcomp_int_enable
* @sa nrf_lpcomp_int_disable
*/
__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t int_mask);
/**
* @brief Function for getting the address of the specified LPCOMP task register.
*
* @param[in] task LPCOMP task.
*
* @return The address of the specified LPCOMP task.
*/
__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t task);
/**
* @brief Function for getting the address of the specified LPCOMP event register.
*
* @param[in] event LPCOMP event.
*
* @return The address of the specified LPCOMP event.
*/
__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t event);
/**
* @brief Function for setting LPCOMP shorts.
*
* @param[in] mask Mask of shortcuts.
*/
__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t mask);
/**
* @brief Function for clearing LPCOMP shorts by mask.
*
* @param[in] mask Mask of shortcuts.
*/
__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t mask);
/**
* @brief Function for setting the specified LPCOMP task.
*
* @param[in] task LPCOMP task to be set.
*/
__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t task);
/**
* @brief Function for clearing the specified LPCOMP event.
*
* @param[in] event LPCOMP event to be cleared.
*/
__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t event);
/**
* @brief Function for retrieving the state of the LPCOMP event.
*
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t event);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config)
{
NRF_LPCOMP->TASKS_STOP = 1;
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
NRF_LPCOMP->REFSEL =
(p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk;
//If external source is choosen extract analog reference index.
if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef)
{
uint32_t extref = p_config->reference >> 16;
NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) &
LPCOMP_EXTREFSEL_EXTREFSEL_Msk;
}
NRF_LPCOMP->ANADETECT =
(p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk;
#ifdef LPCOMP_FEATURE_HYST_PRESENT
NRF_LPCOMP->HYST = ((p_config->hyst) << LPCOMP_HYST_HYST_Pos) & LPCOMP_HYST_HYST_Msk;
#endif //LPCOMP_FEATURE_HYST_PRESENT
NRF_LPCOMP->SHORTS = 0;
NRF_LPCOMP->INTENCLR = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk |
LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk;
}
__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input)
{
uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE;
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
NRF_LPCOMP->PSEL =
((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk);
NRF_LPCOMP->ENABLE = lpcomp_enable_state;
}
__STATIC_INLINE void nrf_lpcomp_enable(void)
{
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos;
NRF_LPCOMP->EVENTS_READY = 0;
NRF_LPCOMP->EVENTS_DOWN = 0;
NRF_LPCOMP->EVENTS_UP = 0;
NRF_LPCOMP->EVENTS_CROSS = 0;
}
__STATIC_INLINE void nrf_lpcomp_disable(void)
{
NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos;
}
__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void)
{
return (uint32_t)NRF_LPCOMP->RESULT;
}
__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t int_mask)
{
NRF_LPCOMP->INTENSET = int_mask;
}
__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t int_mask)
{
NRF_LPCOMP->INTENCLR = int_mask;
}
__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t int_mask)
{
return (NRF_LPCOMP->INTENSET & int_mask); // when read this register will return the value of INTEN.
}
__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t task)
{
return (uint32_t *)((uint8_t *)NRF_LPCOMP + task);
}
__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t event)
{
return (uint32_t *)((uint8_t *)NRF_LPCOMP + event);
}
__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t short_mask)
{
NRF_LPCOMP->SHORTS |= short_mask;
}
__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t short_mask)
{
NRF_LPCOMP->SHORTS &= ~short_mask;
}
__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t task)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + (uint32_t)task) ) = 1;
}
__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t event)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + (uint32_t)event) ) = 0;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t event)
{
return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + (uint32_t)event));
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_LPCOMP_H_

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modules/nrfx/hal/nrf_nfct.h
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modules/nrfx/hal/nrf_pdm.h
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/**
* Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_PDM_H_
#define NRF_PDM_H_
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_pdm_hal PDM HAL
* @{
* @ingroup nrf_pdm
* @brief Hardware access layer for managing the Pulse Density Modulation (PDM) peripheral.
*/
/** @brief Minimum value of PDM gain. */
#define NRF_PDM_GAIN_MINIMUM 0x00
/** @brief Default value of PDM gain. */
#define NRF_PDM_GAIN_DEFAULT 0x28
/** @brief Maximum value of PDM gain. */
#define NRF_PDM_GAIN_MAXIMUM 0x50
/** @brief PDM gain type. */
typedef uint8_t nrf_pdm_gain_t;
/** @brief PDM tasks. */
typedef enum
{
NRF_PDM_TASK_START = offsetof(NRF_PDM_Type, TASKS_START), ///< Starts continuous PDM transfer.
NRF_PDM_TASK_STOP = offsetof(NRF_PDM_Type, TASKS_STOP) ///< Stops PDM transfer.
} nrf_pdm_task_t;
/** @brief PDM events. */
typedef enum
{
NRF_PDM_EVENT_STARTED = offsetof(NRF_PDM_Type, EVENTS_STARTED), ///< PDM transfer is started.
NRF_PDM_EVENT_STOPPED = offsetof(NRF_PDM_Type, EVENTS_STOPPED), ///< PDM transfer is finished.
NRF_PDM_EVENT_END = offsetof(NRF_PDM_Type, EVENTS_END) ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM.
} nrf_pdm_event_t;
/** @brief PDM interrupt masks. */
typedef enum
{
NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event.
NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk, ///< Interrupt on EVENTS_STOPPED event.
NRF_PDM_INT_END = PDM_INTENSET_END_Msk ///< Interrupt on EVENTS_END event.
} nrf_pdm_int_mask_t;
/** @brief PDM clock frequency. */
typedef enum
{
NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K, ///< PDM_CLK = 1.000 MHz.
NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default, ///< PDM_CLK = 1.032 MHz.
NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K ///< PDM_CLK = 1.067 MHz.
} nrf_pdm_freq_t;
/** @brief PDM operation mode. */
typedef enum
{
NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo, ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word.
NRF_PDM_MODE_MONO = PDM_MODE_OPERATION_Mono ///< Sample and store two successive Left samples (16 bit each) per RAM word.
} nrf_pdm_mode_t;
/** @brief PDM sampling mode. */
typedef enum
{
NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling, ///< Left (or mono) is sampled on falling edge of PDM_CLK.
NRF_PDM_EDGE_LEFTRISING = PDM_MODE_EDGE_LeftRising ///< Left (or mono) is sampled on rising edge of PDM_CLK.
} nrf_pdm_edge_t;
/**
* @brief Function for triggering a PDM task.
*
* @param[in] task PDM task.
*/
__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t task);
/**
* @brief Function for getting the address of a PDM task register.
*
* @param[in] task PDM task.
*
* @return Address of the specified PDM task.
*/
__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t task);
/**
* @brief Function for retrieving the state of the PDM event.
*
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t event);
/**
* @brief Function for clearing a PDM event.
*
* @param[in] event PDM event.
*/
__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t event);
/**
* @brief Function for getting the address of a PDM event register.
*
* @param[in] event PDM event.
*
* @return Address of the specified PDM event.
*/
__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t event);
/**
* @brief Function for enabling PDM interrupts.
*
* @param[in] int_mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_pdm_int_enable(uint32_t int_mask);
/**
* @brief Function for retrieving the state of PDM interrupts.
*
* @param[in] int_mask Mask of interrupts to be checked.
*
* @retval true All specified interrupts are enabled.
* @retval false At least one of the given interrupts is not enabled.
*/
__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t int_mask);
/**
* @brief Function for disabling interrupts.
*
* @param[in] int_mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_pdm_int_disable(uint32_t int_mask);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting the subscribe configuration for a given
* PDM task.
*
* @param[in] task Task for which to set the configuration.
* @param[in] channel Channel through which to subscribe events.
*/
__STATIC_INLINE void nrf_pdm_subscribe_set(nrf_pdm_task_t task,
uint8_t channel);
/**
* @brief Function for clearing the subscribe configuration for a given
* PDM task.
*
* @param[in] task Task for which to clear the configuration.
*/
__STATIC_INLINE void nrf_pdm_subscribe_clear(nrf_pdm_task_t task);
/**
* @brief Function for setting the publish configuration for a given
* PDM event.
*
* @param[in] event Event for which to set the configuration.
* @param[in] channel Channel through which to publish the event.
*/
__STATIC_INLINE void nrf_pdm_publish_set(nrf_pdm_event_t event,
uint8_t channel);
/**
* @brief Function for clearing the publish configuration for a given
* PDM event.
*
* @param[in] event Event for which to clear the configuration.
*/
__STATIC_INLINE void nrf_pdm_publish_clear(nrf_pdm_event_t event);
#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for enabling the PDM peripheral.
*
* The PDM peripheral must be enabled before use.
*/
__STATIC_INLINE void nrf_pdm_enable(void);
/** @brief Function for disabling the PDM peripheral. */
__STATIC_INLINE void nrf_pdm_disable(void);
/**
* @brief Function for checking if the PDM peripheral is enabled.
*
* @retval true The PDM peripheral is enabled.
* @retval false The PDM peripheral is not enabled.
*/
__STATIC_INLINE bool nrf_pdm_enable_check(void);
/**
* @brief Function for setting the PDM operation mode.
*
* @param[in] pdm_mode PDM operation mode.
* @param[in] pdm_edge PDM sampling mode.
*/
__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge);
/**
* @brief Function for getting the PDM operation mode.
*
* @param[out] p_pdm_mode PDM operation mode.
* @param[out] p_pdm_edge PDM sampling mode.
*/
__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge);
/**
* @brief Function for setting the PDM clock frequency.
*
* @param[in] pdm_freq PDM clock frequency.
*/
__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq);
/**
* @brief Function for getting the PDM clock frequency.
*
* @return PDM clock frequency.
*/
__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void);
/**
* @brief Function for setting up the PDM pins.
*
* @param[in] psel_clk CLK pin number.
* @param[in] psel_din DIN pin number.
*/
__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din);
/** @brief Function for disconnecting the PDM pins. */
__STATIC_INLINE void nrf_pdm_psel_disconnect(void);
/**
* @brief Function for setting the PDM gain.
*
* @param[in] gain_l Left channel gain.
* @param[in] gain_r Right channel gain.
*/
__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r);
/**
* @brief Function for getting the PDM gain.
*
* @param[out] p_gain_l Left channel gain.
* @param[out] p_gain_r Right channel gain.
*/
__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r);
/**
* @brief Function for setting the PDM sample buffer.
*
* The amount of allocated RAM depends on the operation mode.
* - For stereo mode: N 32-bit words.
* - For mono mode: Ceil(N/2) 32-bit words.
*
* @param[in] p_buffer Pointer to the RAM address where samples are to be written with EasyDMA.
* @param[in] num Number of samples to allocate memory for in EasyDMA mode.
*/
__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num);
/**
* @brief Function for getting the current PDM sample buffer address.
*
* @return Pointer to the current sample buffer.
*/
__STATIC_INLINE uint32_t * nrf_pdm_buffer_get(void);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t task)
{
*((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t task)
{
return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)task);
}
__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event);
}
__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t event)
{
*((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t event)
{
return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)event);
}
__STATIC_INLINE void nrf_pdm_int_enable(uint32_t int_mask)
{
NRF_PDM->INTENSET = int_mask;
}
__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t int_mask)
{
return (bool)(NRF_PDM->INTENSET & int_mask);
}
__STATIC_INLINE void nrf_pdm_int_disable(uint32_t int_mask)
{
NRF_PDM->INTENCLR = int_mask;
}
#if defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_pdm_subscribe_set(nrf_pdm_task_t task,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) NRF_PDM + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | PDM_SUBSCRIBE_START_EN_Msk);
}
__STATIC_INLINE void nrf_pdm_subscribe_clear(nrf_pdm_task_t task)
{
*((volatile uint32_t *) ((uint8_t *) NRF_PDM + (uint32_t) task + 0x80uL)) = 0;
}
__STATIC_INLINE void nrf_pdm_publish_set(nrf_pdm_event_t event,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) NRF_PDM + (uint32_t) event + 0x80uL)) =
((uint32_t)channel | PDM_PUBLISH_STARTED_EN_Msk);
}
__STATIC_INLINE void nrf_pdm_publish_clear(nrf_pdm_event_t event)
{
*((volatile uint32_t *) ((uint8_t *) NRF_PDM + (uint32_t) event + 0x80uL)) = 0;
}
#endif // defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_pdm_enable(void)
{
NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_pdm_disable(void)
{
NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE bool nrf_pdm_enable_check(void)
{
return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos));
}
__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge)
{
NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk)
| ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk);
}
__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge)
{
uint32_t mode = NRF_PDM->MODE;
*p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos);
*p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos);
}
__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq)
{
NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
}
__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void)
{
return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
}
__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din)
{
NRF_PDM->PSEL.CLK = psel_clk;
NRF_PDM->PSEL.DIN = psel_din;
}
__STATIC_INLINE void nrf_pdm_psel_disconnect(void)
{
NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos)
& PDM_PSEL_CLK_CONNECT_Msk);
NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos)
& PDM_PSEL_DIN_CONNECT_Msk);
}
__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r)
{
NRF_PDM->GAINL = gain_l;
NRF_PDM->GAINR = gain_r;
}
__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r)
{
*p_gain_l = NRF_PDM->GAINL;
*p_gain_r = NRF_PDM->GAINR;
}
__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num)
{
NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer;
NRF_PDM->SAMPLE.MAXCNT = num;
}
__STATIC_INLINE uint32_t * nrf_pdm_buffer_get(void)
{
return (uint32_t *)NRF_PDM->SAMPLE.PTR;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_PDM_H_

561
modules/nrfx/hal/nrf_qdec.h
View File

@@ -1,561 +0,0 @@
/**
* Copyright (c) 2014 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_QDEC_H__
#define NRF_QDEC_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_qdec_hal QDEC HAL
* @{
* @ingroup nrf_qdec
* @brief Hardware access layer for managing the Quadrature Decoder (QDEC) peripheral.
*/
/**
* @brief This value can be provided as a parameter for the @ref nrf_qdec_pio_assign
* function call to specify that a LED signal shall not be use by the QDEC and
* connected to a physical pin.
*/
#define NRF_QDEC_LED_NOT_CONNECTED 0xFFFFFFFF
/** @brief QDEC tasks. */
typedef enum
{
NRF_QDEC_TASK_START = offsetof(NRF_QDEC_Type, TASKS_START), /**< Starting the quadrature decoder. */
NRF_QDEC_TASK_STOP = offsetof(NRF_QDEC_Type, TASKS_STOP), /**< Stopping the quadrature decoder. */
NRF_QDEC_TASK_READCLRACC = offsetof(NRF_QDEC_Type, TASKS_READCLRACC) /**< Reading and clearing ACC and ACCDBL registers. */
} nrf_qdec_task_t;
/** @brief QDEC events. */
typedef enum
{
NRF_QDEC_EVENT_SAMPLERDY = offsetof(NRF_QDEC_Type, EVENTS_SAMPLERDY), /**< Event generated for every new sample. */
NRF_QDEC_EVENT_REPORTRDY = offsetof(NRF_QDEC_Type, EVENTS_REPORTRDY), /**< Event generated for every new report. */
NRF_QDEC_EVENT_ACCOF = offsetof(NRF_QDEC_Type, EVENTS_ACCOF) /**< Event generated for every accumulator overflow. */
} nrf_qdec_event_t;
/** @brief QDEC shortcuts. */
typedef enum
{
NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK = QDEC_SHORTS_REPORTRDY_READCLRACC_Msk, /**< Shortcut between REPORTRDY event and READCLRACC task. */
NRF_QDEC_SHORT_SAMPLERDY_STOP_MASK = QDEC_SHORTS_SAMPLERDY_STOP_Msk /**< Shortcut between SAMPLERDY event and STOP task. */
} nrf_qdec_short_mask_t;
/** @brief QDEC interrupts. */
typedef enum
{
NRF_QDEC_INT_SAMPLERDY_MASK = QDEC_INTENSET_SAMPLERDY_Msk, /**< Mask for enabling or disabling an interrupt on SAMPLERDY event. */
NRF_QDEC_INT_REPORTRDY_MASK = QDEC_INTENSET_REPORTRDY_Msk, /**< Mask for enabling or disabling an interrupt on REPORTRDY event. */
NRF_QDEC_INT_ACCOF_MASK = QDEC_INTENSET_ACCOF_Msk /**< Mask for enabling or disabling an interrupt on ACCOF event. */
} nrf_qdec_int_mask_t;
/** @brief States of the enable bit. */
typedef enum
{
NRF_QDEC_DISABLE = QDEC_ENABLE_ENABLE_Disabled, /**< Mask for disabling the QDEC periperal. When disabled, the QDEC decoder pins are not active. */
NRF_QDEC_ENABLE = QDEC_ENABLE_ENABLE_Enabled /**< Mask for enabling the QDEC periperal. When enabled, the QDEC pins are active. */
} nrf_qdec_enable_t;
/** @brief States of the debounce filter enable bit. */
typedef enum
{
NRF_QDEC_DBFEN_DISABLE = QDEC_DBFEN_DBFEN_Disabled, /**< Mask for disabling the debounce filter. */
NRF_QDEC_DBFEN_ENABLE = QDEC_DBFEN_DBFEN_Enabled /**< Mask for enabling the debounce filter. */
} nrf_qdec_dbfen_t;
/** @brief Active LED polarity. */
typedef enum
{
NRF_QDEC_LEPOL_ACTIVE_LOW = QDEC_LEDPOL_LEDPOL_ActiveLow, /**< QDEC LED active on output pin low. */
NRF_QDEC_LEPOL_ACTIVE_HIGH = QDEC_LEDPOL_LEDPOL_ActiveHigh /**< QDEC LED active on output pin high. */
} nrf_qdec_ledpol_t;
/** @brief Available sampling periods. */
typedef enum
{
NRF_QDEC_SAMPLEPER_128us = QDEC_SAMPLEPER_SAMPLEPER_128us, /**< QDEC sampling period 128 microseconds. */
NRF_QDEC_SAMPLEPER_256us = QDEC_SAMPLEPER_SAMPLEPER_256us, /**< QDEC sampling period 256 microseconds. */
NRF_QDEC_SAMPLEPER_512us = QDEC_SAMPLEPER_SAMPLEPER_512us, /**< QDEC sampling period 512 microseconds. */
NRF_QDEC_SAMPLEPER_1024us = QDEC_SAMPLEPER_SAMPLEPER_1024us, /**< QDEC sampling period 1024 microseconds. */
NRF_QDEC_SAMPLEPER_2048us = QDEC_SAMPLEPER_SAMPLEPER_2048us, /**< QDEC sampling period 2048 microseconds. */
NRF_QDEC_SAMPLEPER_4096us = QDEC_SAMPLEPER_SAMPLEPER_4096us, /**< QDEC sampling period 4096 microseconds. */
NRF_QDEC_SAMPLEPER_8192us = QDEC_SAMPLEPER_SAMPLEPER_8192us, /**< QDEC sampling period 8192 microseconds. */
NRF_QDEC_SAMPLEPER_16384us = QDEC_SAMPLEPER_SAMPLEPER_16384us /**< QDEC sampling period 16384 microseconds. */
} nrf_qdec_sampleper_t;
/** @brief Available report periods. */
typedef enum
{
#if defined(QDEC_REPORTPER_REPORTPER_1Smpl) || defined(__NRFX_DOXYGEN__)
NRF_QDEC_REPORTPER_1 = QDEC_REPORTPER_REPORTPER_1Smpl, /**< QDEC report period 1 sample. */
#endif
NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */
NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */
NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */
NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */
NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */
NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */
NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */
NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */
NRF_QDEC_REPORTPER_DISABLED = (QDEC_REPORTPER_REPORTPER_Msk >> QDEC_REPORTPER_REPORTPER_Pos) + 1 /**< QDEC reporting disabled. Deprecated. */
} nrf_qdec_reportper_t;
/** @brief Function for enabling QDEC. */
__STATIC_INLINE void nrf_qdec_enable(void);
/** @brief Function for disabling QDEC. */
__STATIC_INLINE void nrf_qdec_disable(void);
/**
* @brief Function for returning the enable state of QDEC.
*
* @return State of the register.
*/
__STATIC_INLINE uint32_t nrf_qdec_enable_get(void);
/**
* @brief Function for enabling QDEC interrupts by mask.
*
* @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_qdec_int_enable(uint32_t mask);
/**
* @brief Function for disabling QDEC interrupts by mask.
*
* @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_qdec_int_disable(uint32_t mask);
/**
* @brief Function for getting the enabled interrupts of the QDEC.
*
* @param[in] mask Mask of interrupts to be checked.
*
* @return Bitfield with enabled interrupts.
*/
__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t mask);
/** @brief Function for enabling the QDEC debouncing filter. */
__STATIC_INLINE void nrf_qdec_dbfen_enable(void);
/** @brief Function for disabling the QDEC debouncing filter. */
__STATIC_INLINE void nrf_qdec_dbfen_disable(void);
/**
* @brief Function for getting the state of the QDEC debouncing filter.
*
* @retval NRF_QDEC_DBFEN_DISABLE The debouncing filter is disabled.
* @retval NRF_QDEC_DBFEN_ENABLE The debouncing filter is enabled.
*/
__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void);
/**
* @brief Function for assigning QDEC pins.
*
* @param[in] psela Pin number.
* @param[in] pselb Pin number.
* @param[in] pselled Pin number.
*/
__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled);
/**
* @brief Function for setting the specified QDEC task.
*
* @param[in] task QDEC task to be triggered.
*/
__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t task);
/**
* @brief Function for retrieving the address of a QDEC task register.
*
* @param[in] task QDEC task to get its address.
*
* @return Address of the specified QDEC task.
*/
__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t task);
/**
* @brief Function for clearing the specified QDEC event.
*
* @param[in] event QDEC event to be cleared.
*/
__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t event);
/**
* @brief Function for getting the state of the specified QDEC event.
*
* @param[in] event QDEC event to be checked.
*
* @return State of the specified QDEC event.
*/
__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t event);
/**
* @brief Function for retrieving the address of the specified QDEC event register.
*
* @param[in] event QDEC event to get its address.
*
* @return Address of the specified QDEC event.
*/
__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t event);
/**
* @brief Function for setting QDEC shortcuts.
*
* @param[in] mask Mask of QDEC shortcuts to be set.
*/
__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t mask);
/**
* @brief Function for clearing shortcuts of the QDEC by mask.
*
* @param[in] mask Mask of QDEC shortcuts to be cleared.
*/
__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t mask);
/**
* @brief Function for retrieving value of the sampling period.
*
* @return Sample period @ref nrf_qdec_sampleper_t.
*/
__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void);
/**
* @brief Function for converting return value of the @p nrf_qdec_sampleper_reg_get() function
* to microseconds.
*
* @param[in] sampleper The sampling period.
*
* @return Period in microseconds.
*/
__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper);
/**
* @brief Function for setting value of the QDEC sampling period.
*
* @param[in] sample_per The sampling period.
*/
__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per);
/**
* @brief Function for retrieving value of the QDEC SAMPLE register.
*
* @return Value of the SAMPLE register.
*/
__STATIC_INLINE int32_t nrf_qdec_sample_get(void);
/**
* @brief Function for retrieving value of the QDEC ACC register.
*
* @return Value of the ACC register.
*/
__STATIC_INLINE int32_t nrf_qdec_acc_get(void);
/**
* @brief Function for retrieving value of the QDEC ACCREAD register.
*
* @return Value of the ACCREAD register.
*/
__STATIC_INLINE int32_t nrf_qdec_accread_get(void);
/**
* @brief Function for retrieving value of the QDEC ACCDBL register.
*
* @return Value of the ACCDBL register.
*/
__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void);
/**
* @brief Function for retrieving value of the QDEC ACCDBLREAD register.
*
* @return Value of the ACCDBLREAD register.
*/
__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void);
/**
* @brief Function for setting delay time between setting LED active state and start sampling.
*
* @param[in] time_us Delay time (in microseconds) between setting LED active state
* and start sampling.
*/
__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us);
/**
* @brief Function for retrieving how long the LED is switched on before sampling.
*
* @return The gap in time in microseconds between switched LED to active state and start sampling.
*/
__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void);
/**
* @brief Function for setting the report period (in samples).
*
* @param[in] reportper The number of samples.
*/
__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper);
/**
* @brief Function for retrieving the report period.
*
* @return The report period.
*/
__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void);
/**
* @brief Function for retrieving the value of QDEC SAMPLEPER register.
*
* @param [in] reportper Reportper to be converted to amount of samples per report.
*
* @return Number of samples per report.
*/
__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper);
/**
* @brief Function for setting the active level for the LED.
*
* @param[in] pol Level of the active signal of the LED.
*/
__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol);
/**
* @brief Function for retrieving the active level for the LED.
*
* @return Level of the active signal of the LED.
*/
__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_qdec_enable(void)
{
NRF_QDEC->ENABLE = NRF_QDEC_ENABLE;
}
__STATIC_INLINE void nrf_qdec_disable(void)
{
NRF_QDEC->ENABLE = NRF_QDEC_DISABLE;
}
__STATIC_INLINE uint32_t nrf_qdec_enable_get(void)
{
return NRF_QDEC->ENABLE;
}
__STATIC_INLINE void nrf_qdec_int_enable(uint32_t mask)
{
NRF_QDEC->INTENSET = mask; // writing 0 has no effect
}
__STATIC_INLINE void nrf_qdec_int_disable(uint32_t mask)
{
NRF_QDEC->INTENCLR = mask; // writing 0 has no effect
}
__STATIC_INLINE uint32_t nrf_qdec_int_enable_check(nrf_qdec_int_mask_t mask)
{
return NRF_QDEC->INTENSET & mask; // when read this register will return the value of INTEN.
}
__STATIC_INLINE void nrf_qdec_dbfen_enable(void)
{
NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_ENABLE;
}
__STATIC_INLINE void nrf_qdec_dbfen_disable(void)
{
NRF_QDEC->DBFEN = NRF_QDEC_DBFEN_DISABLE;
}
__STATIC_INLINE uint32_t nrf_qdec_dbfen_get(void)
{
return NRF_QDEC->DBFEN;
}
__STATIC_INLINE void nrf_qdec_pio_assign( uint32_t psela, uint32_t pselb, uint32_t pselled)
{
#if defined(QDEC_PSEL_A_CONNECT_Pos)
NRF_QDEC->PSEL.A = psela;
#else
NRF_QDEC->PSELA = psela;
#endif
#if defined(QDEC_PSEL_B_CONNECT_Pos)
NRF_QDEC->PSEL.B = pselb;
#else
NRF_QDEC->PSELB = pselb;
#endif
#if defined(QDEC_PSEL_LED_CONNECT_Pos)
NRF_QDEC->PSEL.LED = pselled;
#else
NRF_QDEC->PSELLED = pselled;
#endif
}
__STATIC_INLINE void nrf_qdec_task_trigger(nrf_qdec_task_t task)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)task) ) = 1;
}
__STATIC_INLINE uint32_t * nrf_qdec_task_address_get(nrf_qdec_task_t task)
{
return (uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)task);
}
__STATIC_INLINE void nrf_qdec_event_clear(nrf_qdec_event_t event)
{
*( (volatile uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)event) ) = 0;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_QDEC + event));
(void)dummy;
#endif
}
__STATIC_INLINE uint32_t nrf_qdec_event_check(nrf_qdec_event_t event)
{
return *(volatile uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)event);
}
__STATIC_INLINE uint32_t * nrf_qdec_event_address_get(nrf_qdec_event_t event)
{
return (uint32_t *)( (uint8_t *)NRF_QDEC + (uint32_t)event);
}
__STATIC_INLINE void nrf_qdec_shorts_enable(uint32_t mask)
{
NRF_QDEC->SHORTS |= mask;
}
__STATIC_INLINE void nrf_qdec_shorts_disable(uint32_t mask)
{
NRF_QDEC->SHORTS &= ~mask;
}
__STATIC_INLINE int32_t nrf_qdec_sampleper_reg_get(void)
{
return NRF_QDEC->SAMPLEPER;
}
__STATIC_INLINE uint32_t nrf_qdec_sampleper_to_value(uint32_t sampleper)
{
return (1 << (7 + sampleper));
}
__STATIC_INLINE void nrf_qdec_sampleper_set(nrf_qdec_sampleper_t sample_per)
{
NRF_QDEC->SAMPLEPER = sample_per;
}
__STATIC_INLINE int32_t nrf_qdec_sample_get(void)
{
return NRF_QDEC->SAMPLE;
}
__STATIC_INLINE int32_t nrf_qdec_acc_get(void)
{
return NRF_QDEC->ACC;
}
__STATIC_INLINE int32_t nrf_qdec_accread_get(void)
{
return NRF_QDEC->ACCREAD;
}
__STATIC_INLINE uint32_t nrf_qdec_accdbl_get(void)
{
return NRF_QDEC->ACCDBL;
}
__STATIC_INLINE uint32_t nrf_qdec_accdblread_get(void)
{
return NRF_QDEC->ACCDBLREAD;
}
__STATIC_INLINE void nrf_qdec_ledpre_set(uint32_t time_us)
{
NRF_QDEC->LEDPRE = time_us;
}
__STATIC_INLINE uint32_t nrf_qdec_ledpre_get(void)
{
return NRF_QDEC->LEDPRE;
}
__STATIC_INLINE void nrf_qdec_reportper_set(nrf_qdec_reportper_t reportper)
{
NRF_QDEC->REPORTPER = reportper;
}
__STATIC_INLINE uint32_t nrf_qdec_reportper_reg_get(void)
{
return NRF_QDEC->REPORTPER;
}
__STATIC_INLINE uint32_t nrf_qdec_reportper_to_value(uint32_t reportper)
{
return (reportper == NRF_QDEC_REPORTPER_10) ? 10 : reportper * 40;
}
__STATIC_INLINE void nrf_qdec_ledpol_set(nrf_qdec_ledpol_t pol)
{
NRF_QDEC->LEDPOL = pol;
}
__STATIC_INLINE uint32_t nrf_qdec_ledpol_get(void)
{
return NRF_QDEC->LEDPOL;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_QDEC_H__

823
modules/nrfx/hal/nrf_qspi.h
View File

@@ -1,823 +0,0 @@
/**
* Copyright (c) 2016 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_QSPI_H__
#define NRF_QSPI_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_qspi_hal QSPI HAL
* @{
* @ingroup nrf_qspi
* @brief Hardware access layer for managing the QSPI peripheral.
*/
/**
* @brief This value can be used as a parameter for the @ref nrf_qspi_pins_set
* function to specify that a given QSPI signal (SCK, CSN, IO0, IO1, IO2, or IO3)
* will not be connected to a physical pin.
*/
#define NRF_QSPI_PIN_NOT_CONNECTED 0xFF
/** @brief Macro for setting proper values to pin registers. */
#define NRF_QSPI_PIN_VAL(pin) (pin) == NRF_QSPI_PIN_NOT_CONNECTED ? 0xFFFFFFFF : (pin)
/** @brief QSPI tasks. */
typedef enum
{
NRF_QSPI_TASK_ACTIVATE = offsetof(NRF_QSPI_Type, TASKS_ACTIVATE), /**< Activate the QSPI interface. */
NRF_QSPI_TASK_READSTART = offsetof(NRF_QSPI_Type, TASKS_READSTART), /**< Start transfer from external flash memory to internal RAM. */
NRF_QSPI_TASK_WRITESTART = offsetof(NRF_QSPI_Type, TASKS_WRITESTART), /**< Start transfer from internal RAM to external flash memory. */
NRF_QSPI_TASK_ERASESTART = offsetof(NRF_QSPI_Type, TASKS_ERASESTART), /**< Start external flash memory erase operation. */
NRF_QSPI_TASK_DEACTIVATE = offsetof(NRF_QSPI_Type, TASKS_DEACTIVATE), /**< Deactivate the QSPI interface. */
} nrf_qspi_task_t;
/** @brief QSPI events. */
typedef enum
{
NRF_QSPI_EVENT_READY = offsetof(NRF_QSPI_Type, EVENTS_READY) /**< QSPI peripheral is ready after it executes any task. */
} nrf_qspi_event_t;
/** @brief QSPI interrupts. */
typedef enum
{
NRF_QSPI_INT_READY_MASK = QSPI_INTENSET_READY_Msk /**< Interrupt on READY event. */
} nrf_qspi_int_mask_t;
/** @brief QSPI frequency divider values. */
typedef enum
{
NRF_QSPI_FREQ_32MDIV1, /**< 32.0 MHz. */
NRF_QSPI_FREQ_32MDIV2, /**< 16.0 MHz. */
NRF_QSPI_FREQ_32MDIV3, /**< 10.6 MHz. */
NRF_QSPI_FREQ_32MDIV4, /**< 8.00 MHz. */
NRF_QSPI_FREQ_32MDIV5, /**< 6.40 MHz. */
NRF_QSPI_FREQ_32MDIV6, /**< 5.33 MHz. */
NRF_QSPI_FREQ_32MDIV7, /**< 4.57 MHz. */
NRF_QSPI_FREQ_32MDIV8, /**< 4.00 MHz. */
NRF_QSPI_FREQ_32MDIV9, /**< 3.55 MHz. */
NRF_QSPI_FREQ_32MDIV10, /**< 3.20 MHz. */
NRF_QSPI_FREQ_32MDIV11, /**< 2.90 MHz. */
NRF_QSPI_FREQ_32MDIV12, /**< 2.66 MHz. */
NRF_QSPI_FREQ_32MDIV13, /**< 2.46 MHz. */
NRF_QSPI_FREQ_32MDIV14, /**< 2.29 MHz. */
NRF_QSPI_FREQ_32MDIV15, /**< 2.13 MHz. */
NRF_QSPI_FREQ_32MDIV16, /**< 2.00 MHz. */
} nrf_qspi_frequency_t;
/** @brief Interface configuration for a read operation. */
typedef enum
{
NRF_QSPI_READOC_FASTREAD = QSPI_IFCONFIG0_READOC_FASTREAD, /**< Single data line SPI. FAST_READ (opcode 0x0B). */
NRF_QSPI_READOC_READ2O = QSPI_IFCONFIG0_READOC_READ2O, /**< Dual data line SPI. READ2O (opcode 0x3B). */
NRF_QSPI_READOC_READ2IO = QSPI_IFCONFIG0_READOC_READ2IO, /**< Dual data line SPI. READ2IO (opcode 0xBB). */
NRF_QSPI_READOC_READ4O = QSPI_IFCONFIG0_READOC_READ4O, /**< Quad data line SPI. READ4O (opcode 0x6B). */
NRF_QSPI_READOC_READ4IO = QSPI_IFCONFIG0_READOC_READ4IO /**< Quad data line SPI. READ4IO (opcode 0xEB). */
} nrf_qspi_readoc_t;
/** @brief Interface configuration for a write operation. */
typedef enum
{
NRF_QSPI_WRITEOC_PP = QSPI_IFCONFIG0_WRITEOC_PP, /**< Single data line SPI. PP (opcode 0x02). */
NRF_QSPI_WRITEOC_PP2O = QSPI_IFCONFIG0_WRITEOC_PP2O, /**< Dual data line SPI. PP2O (opcode 0xA2). */
NRF_QSPI_WRITEOC_PP4O = QSPI_IFCONFIG0_WRITEOC_PP4O, /**< Quad data line SPI. PP4O (opcode 0x32). */
NRF_QSPI_WRITEOC_PP4IO = QSPI_IFCONFIG0_WRITEOC_PP4IO, /**< Quad data line SPI. READ4O (opcode 0x38). */
} nrf_qspi_writeoc_t;
/** @brief Interface configuration for addressing mode. */
typedef enum
{
NRF_QSPI_ADDRMODE_24BIT = QSPI_IFCONFIG0_ADDRMODE_24BIT, /**< 24-bit addressing. */
NRF_QSPI_ADDRMODE_32BIT = QSPI_IFCONFIG0_ADDRMODE_32BIT /**< 32-bit addressing. */
} nrf_qspi_addrmode_t;
/** @brief QSPI SPI mode. Polarization and phase configuration. */
typedef enum
{
NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
} nrf_qspi_spi_mode_t;
/** @brief Addressing configuration mode. */
typedef enum
{
NRF_QSPI_ADDRCONF_MODE_NOINSTR = QSPI_ADDRCONF_MODE_NoInstr, /**< Do not send any instruction. */
NRF_QSPI_ADDRCONF_MODE_OPCODE = QSPI_ADDRCONF_MODE_Opcode, /**< Send opcode. */
NRF_QSPI_ADDRCONF_MODE_OPBYTE0 = QSPI_ADDRCONF_MODE_OpByte0, /**< Send opcode, byte0. */
NRF_QSPI_ADDRCONF_MODE_ALL = QSPI_ADDRCONF_MODE_All /**< Send opcode, byte0, byte1. */
} nrf_qspi_addrconfig_mode_t;
/** @brief Erasing data length. */
typedef enum
{
NRF_QSPI_ERASE_LEN_4KB = QSPI_ERASE_LEN_LEN_4KB, /**< Erase 4 kB block (flash command 0x20). */
NRF_QSPI_ERASE_LEN_64KB = QSPI_ERASE_LEN_LEN_64KB, /**< Erase 64 kB block (flash command 0xD8). */
NRF_QSPI_ERASE_LEN_ALL = QSPI_ERASE_LEN_LEN_All /**< Erase all (flash command 0xC7). */
} nrf_qspi_erase_len_t;
/** @brief Custom instruction length. */
typedef enum
{
NRF_QSPI_CINSTR_LEN_1B = QSPI_CINSTRCONF_LENGTH_1B, /**< Send opcode only. */
NRF_QSPI_CINSTR_LEN_2B = QSPI_CINSTRCONF_LENGTH_2B, /**< Send opcode, CINSTRDAT0.BYTE0. */
NRF_QSPI_CINSTR_LEN_3B = QSPI_CINSTRCONF_LENGTH_3B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. */
NRF_QSPI_CINSTR_LEN_4B = QSPI_CINSTRCONF_LENGTH_4B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. */
NRF_QSPI_CINSTR_LEN_5B = QSPI_CINSTRCONF_LENGTH_5B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. */
NRF_QSPI_CINSTR_LEN_6B = QSPI_CINSTRCONF_LENGTH_6B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. */
NRF_QSPI_CINSTR_LEN_7B = QSPI_CINSTRCONF_LENGTH_7B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. */
NRF_QSPI_CINSTR_LEN_8B = QSPI_CINSTRCONF_LENGTH_8B, /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. */
NRF_QSPI_CINSTR_LEN_9B = QSPI_CINSTRCONF_LENGTH_9B /**< Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. */
} nrf_qspi_cinstr_len_t;
/** @brief Pin configuration. */
typedef struct
{
uint8_t sck_pin; /**< SCK pin number. */
uint8_t csn_pin; /**< Chip select pin number. */
uint8_t io0_pin; /**< IO0/MOSI pin number. */
uint8_t io1_pin; /**< IO1/MISO pin number. */
uint8_t io2_pin; /**< IO2 pin number (optional).
* Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
*/
uint8_t io3_pin; /**< IO3 pin number (optional).
* Set to @ref NRF_QSPI_PIN_NOT_CONNECTED if this signal is not needed.
*/
} nrf_qspi_pins_t;
/** @brief Custom instruction configuration. */
typedef struct
{
uint8_t opcode; /**< Opcode used in custom instruction transmission. */
nrf_qspi_cinstr_len_t length; /**< Length of the custom instruction data. */
bool io2_level; /**< I/O line level during transmission. */
bool io3_level; /**< I/O line level during transmission. */
bool wipwait; /**< Wait if a Wait in Progress bit is set in the memory status byte. */
bool wren; /**< Send write enable before instruction. */
} nrf_qspi_cinstr_conf_t;
/** @brief Addressing mode register configuration. See @ref nrf_qspi_addrconfig_set */
typedef struct
{
uint8_t opcode; /**< Opcode used to enter the proper addressing mode. */
uint8_t byte0; /**< Byte following the opcode. */
uint8_t byte1; /**< Byte following byte0. */
nrf_qspi_addrconfig_mode_t mode; /**< Extended addresing mode. */
bool wipwait; /**< Enable or disable waiting for complete operation execution. */
bool wren; /**< Send write enable before instruction. */
} nrf_qspi_addrconfig_conf_t;
/** @brief Structure with QSPI protocol interface configuration. */
typedef struct
{
nrf_qspi_readoc_t readoc; /**< Read operation code. */
nrf_qspi_writeoc_t writeoc; /**< Write operation code. */
nrf_qspi_addrmode_t addrmode; /**< Addresing mode (24-bit or 32-bit). */
bool dpmconfig; /**< Enable the Deep Power-down Mode (DPM) feature. */
} nrf_qspi_prot_conf_t;
/** @brief QSPI physical interface configuration. */
typedef struct
{
uint8_t sck_delay; /**< tSHSL, tWHSL, and tSHWL in number of 16 MHz periods (62.5ns). */
bool dpmen; /**< Enable the DPM feature. */
nrf_qspi_spi_mode_t spi_mode; /**< SPI phase and polarization. */
nrf_qspi_frequency_t sck_freq; /**< SCK frequency given as enum @ref nrf_qspi_frequency_t. */
} nrf_qspi_phy_conf_t;
/**
* @brief Function for activating the specified QSPI task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task);
/**
* @brief Function for getting the address of the specified QSPI task register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task QSPI task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_task_t task);
/**
* @brief Function for clearing the specified QSPI event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be cleared.
*/
__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event);
/**
* @brief Function for retrieving the state of the QSPI event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event);
/**
* @brief Function for getting the address of the specified QSPI event register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_event_t event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] qspi_int Interrupt to be checked.
*
* @retval true The interrupt is enabled.
* @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
nrf_qspi_int_mask_t qspi_int);
/**
* @brief Function for enabling the QSPI peripheral.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg);
/**
* @brief Function for disabling the QSPI peripheral.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
/**
* @brief Function for configuring QSPI pins.
*
* If a given signal is not needed, pass the @ref NRF_QSPI_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_pins Pointer to the pins configuration structure. See @ref nrf_qspi_pins_t.
*/
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_pins_t * p_pins);
/**
* @brief Function for getting the currently configured QSPI pins.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[out] p_pins Pointer to the pins configuration structure to be filled with QSPI pins.
*/
__STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_pins_t * p_pins);
/**
* @brief Function for setting the QSPI XIPOFFSET register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] xip_offset Address offset in the external memory for Execute in Place operation.
*/
__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
uint32_t xip_offset);
/**
* @brief Function for setting the QSPI IFCONFIG0 register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_config Pointer to the QSPI protocol interface configuration structure.
* See @ref nrf_qspi_prot_conf_t.
*/
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_prot_conf_t * p_config);
/**
* @brief Function for setting the QSPI IFCONFIG1 register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_config Pointer to the QSPI physical interface configuration structure.
* See @ref nrf_qspi_phy_conf_t.
*/
__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_phy_conf_t * p_config);
/**
* @brief Function for setting the QSPI ADDRCONF register.
*
* This function must be executed before sending task NRF_QSPI_TASK_ACTIVATE. Data stored in the structure
* is sent during the start of the peripheral. Remember that the reset instruction can set
* addressing mode to default in the memory device. If memory reset is necessary before configuring
* the addressing mode, use custom instruction feature instead of this function.
* Case with reset: Enable the peripheral without setting ADDRCONF register, send reset instructions
* using a custom instruction feature (reset enable and then reset), set proper addressing mode
* using the custom instruction feature.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_config Pointer to the addressing mode configuration structure.
* See @ref nrf_qspi_addrconfig_conf_t.
*/
__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_addrconfig_conf_t * p_config);
/**
* @brief Function for setting write data into the peripheral register (without starting the process).
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the writing buffer.
* @param[in] length Lenght of the writing data.
* @param[in] dest_addr Address in memory to write to.
*/
__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
void const * p_buffer,
uint32_t length,
uint32_t dest_addr);
/**
* @brief Function for setting read data into the peripheral register (without starting the process).
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[out] p_buffer Pointer to the reading buffer.
* @param[in] length Length of the read data.
* @param[in] src_addr Address in memory to read from.
*/
__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
void * p_buffer,
uint32_t length,
uint32_t src_addr);
/**
* @brief Function for setting erase data into the peripheral register (without starting the process).
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] erase_addr Start address to erase. Address must have padding set to 4 bytes.
* @param[in] len Size of erasing area.
*/
__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
uint32_t erase_addr,
nrf_qspi_erase_len_t len);
/**
* @brief Function for getting the peripheral status register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Peripheral status register.
*/
__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for getting the device status register stored in the peripheral status register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Device status register (lower byte).
*/
__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for checking if the peripheral is busy or not.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval true The QSPI is busy.
* @retval false The QSPI is ready.
*/
__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for setting registers sending with custom instruction transmission.
*
* This function can be ommited when using NRF_QSPI_CINSTR_LEN_1B as the length argument
* (sending only opcode without data).
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] length Length of the custom instruction data.
* @param[in] p_tx_data Pointer to the data to send with the custom instruction.
*/
__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
nrf_qspi_cinstr_len_t length,
void const * p_tx_data);
/**
* @brief Function for getting data from register after custom instruction transmission.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] length Length of the custom instruction data.
* @param[in] p_rx_data Pointer to the reading buffer.
*/
__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_cinstr_len_t length,
void * p_rx_data);
/**
* @brief Function for sending custom instruction to external memory.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_config Pointer to the custom instruction configuration structure.
* See @ref nrf_qspi_cinstr_conf_t.
*/
__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
const nrf_qspi_cinstr_conf_t * p_config);
/**
* @brief Function for starting a custom instruction long transfer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_config Pointer to the custom instruction configuration structure.
* See @ref nrf_qspi_cinstr_conf_t.
*/
__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
const nrf_qspi_cinstr_conf_t * p_config);
/**
* @brief Function for checking whether a custom instruction long transfer is ongoing.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @retval true Custom instruction long transfer is ongoing.
* @retval false Custom instruction long transfer is not ongoing.
*/
__STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg);
/**
* @brief Function for continuing a custom instruction long transfer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] length Length of the custom instruction data.
* @param[in] finalize True if the custom instruction long transfer is to be finalized.
* False if the custom instruction long transfer is to be continued.
*/
__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
nrf_qspi_cinstr_len_t length,
bool finalize);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_qspi_task_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_task_t task)
{
return ((uint32_t)p_reg + (uint32_t)task);
}
__STATIC_INLINE void nrf_qspi_event_clear(NRF_QSPI_Type * p_reg, nrf_qspi_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_qspi_event_check(NRF_QSPI_Type const * p_reg, nrf_qspi_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE uint32_t * nrf_qspi_event_address_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_event_t event)
{
return (uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_qspi_int_enable(NRF_QSPI_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_qspi_int_disable(NRF_QSPI_Type * p_reg, uint32_t mask)
{
p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_qspi_int_enable_check(NRF_QSPI_Type const * p_reg,
nrf_qspi_int_mask_t qspi_int)
{
return (bool)(p_reg->INTENSET & qspi_int);
}
__STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
{
p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Enabled << QSPI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
{
// Workaround for nRF52840 anomaly 122: Current consumption is too high.
*(volatile uint32_t *)0x40029054ul = 1ul;
p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pins_t * p_pins)
{
p_reg->PSEL.SCK = NRF_QSPI_PIN_VAL(p_pins->sck_pin);
p_reg->PSEL.CSN = NRF_QSPI_PIN_VAL(p_pins->csn_pin);
p_reg->PSEL.IO0 = NRF_QSPI_PIN_VAL(p_pins->io0_pin);
p_reg->PSEL.IO1 = NRF_QSPI_PIN_VAL(p_pins->io1_pin);
p_reg->PSEL.IO2 = NRF_QSPI_PIN_VAL(p_pins->io2_pin);
p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
}
__STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_pins_t * p_pins)
{
p_pins->sck_pin = (uint8_t)p_reg->PSEL.SCK;
p_pins->csn_pin = (uint8_t)p_reg->PSEL.CSN;
p_pins->io0_pin = (uint8_t)p_reg->PSEL.IO0;
p_pins->io1_pin = (uint8_t)p_reg->PSEL.IO1;
p_pins->io2_pin = (uint8_t)p_reg->PSEL.IO2;
p_pins->io3_pin = (uint8_t)p_reg->PSEL.IO3;
}
__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
uint32_t xip_offset)
{
p_reg->XIPOFFSET = xip_offset;
}
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_prot_conf_t * p_config)
{
uint32_t config = p_config->readoc;
config |= ((uint32_t)p_config->writeoc) << QSPI_IFCONFIG0_WRITEOC_Pos;
config |= ((uint32_t)p_config->addrmode) << QSPI_IFCONFIG0_ADDRMODE_Pos;
config |= (p_config->dpmconfig ? 1U : 0U ) << QSPI_IFCONFIG0_DPMENABLE_Pos;
p_reg->IFCONFIG0 = config;
}
__STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_phy_conf_t * p_config)
{
// IFCONFIG1 mask for reserved fields in the register.
uint32_t config = p_reg->IFCONFIG1 & 0x00FFFF00;
config |= p_config->sck_delay;
config |= (p_config->dpmen ? 1U : 0U) << QSPI_IFCONFIG1_DPMEN_Pos;
config |= ((uint32_t)(p_config->spi_mode)) << QSPI_IFCONFIG1_SPIMODE_Pos;
config |= ((uint32_t)(p_config->sck_freq)) << QSPI_IFCONFIG1_SCKFREQ_Pos;
p_reg->IFCONFIG1 = config;
}
__STATIC_INLINE void nrf_qspi_addrconfig_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_addrconfig_conf_t * p_config)
{
uint32_t config = p_config->opcode;
config |= ((uint32_t)p_config->byte0) << QSPI_ADDRCONF_BYTE0_Pos;
config |= ((uint32_t)p_config->byte1) << QSPI_ADDRCONF_BYTE1_Pos;
config |= ((uint32_t)(p_config->mode)) << QSPI_ADDRCONF_MODE_Pos;
config |= (p_config->wipwait ? 1U : 0U) << QSPI_ADDRCONF_WIPWAIT_Pos;
config |= (p_config->wren ? 1U : 0U) << QSPI_ADDRCONF_WREN_Pos;
p_reg->ADDRCONF = config;
}
__STATIC_INLINE void nrf_qspi_write_buffer_set(NRF_QSPI_Type * p_reg,
void const * p_buffer,
uint32_t length,
uint32_t dest_addr)
{
p_reg->WRITE.DST = dest_addr;
p_reg->WRITE.SRC = (uint32_t) p_buffer;
p_reg->WRITE.CNT = length;
}
__STATIC_INLINE void nrf_qspi_read_buffer_set(NRF_QSPI_Type * p_reg,
void * p_buffer,
uint32_t length,
uint32_t src_addr)
{
p_reg->READ.SRC = src_addr;
p_reg->READ.DST = (uint32_t) p_buffer;
p_reg->READ.CNT = length;
}
__STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg,
uint32_t erase_addr,
nrf_qspi_erase_len_t len)
{
p_reg->ERASE.PTR = erase_addr;
p_reg->ERASE.LEN = len;
}
__STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg)
{
return p_reg->STATUS;
}
__STATIC_INLINE uint8_t nrf_qspi_sreg_get(NRF_QSPI_Type const * p_reg)
{
return (uint8_t)(p_reg->STATUS & QSPI_STATUS_SREG_Msk) >> QSPI_STATUS_SREG_Pos;
}
__STATIC_INLINE bool nrf_qspi_busy_check(NRF_QSPI_Type const * p_reg)
{
return ((p_reg->STATUS & QSPI_STATUS_READY_Msk) >>
QSPI_STATUS_READY_Pos) == QSPI_STATUS_READY_BUSY;
}
__STATIC_INLINE void nrf_qspi_cinstrdata_set(NRF_QSPI_Type * p_reg,
nrf_qspi_cinstr_len_t length,
void const * p_tx_data)
{
uint32_t reg = 0;
uint8_t const *p_tx_data_8 = (uint8_t const *) p_tx_data;
// Load custom instruction.
switch (length)
{
case NRF_QSPI_CINSTR_LEN_9B:
reg |= ((uint32_t)p_tx_data_8[7]) << QSPI_CINSTRDAT1_BYTE7_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_8B:
reg |= ((uint32_t)p_tx_data_8[6]) << QSPI_CINSTRDAT1_BYTE6_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_7B:
reg |= ((uint32_t)p_tx_data_8[5]) << QSPI_CINSTRDAT1_BYTE5_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_6B:
reg |= ((uint32_t)p_tx_data_8[4]);
p_reg->CINSTRDAT1 = reg;
reg = 0;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_5B:
reg |= ((uint32_t)p_tx_data_8[3]) << QSPI_CINSTRDAT0_BYTE3_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_4B:
reg |= ((uint32_t)p_tx_data_8[2]) << QSPI_CINSTRDAT0_BYTE2_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_3B:
reg |= ((uint32_t)p_tx_data_8[1]) << QSPI_CINSTRDAT0_BYTE1_Pos;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_2B:
reg |= ((uint32_t)p_tx_data_8[0]);
p_reg->CINSTRDAT0 = reg;
/* fall-through */
case NRF_QSPI_CINSTR_LEN_1B:
/* Send only opcode. Case to avoid compiler warnings. */
break;
default:
break;
}
}
__STATIC_INLINE void nrf_qspi_cinstrdata_get(NRF_QSPI_Type const * p_reg,
nrf_qspi_cinstr_len_t length,
void * p_rx_data)
{
uint8_t *p_rx_data_8 = (uint8_t *) p_rx_data;
uint32_t reg1 = p_reg->CINSTRDAT1;
uint32_t reg0 = p_reg->CINSTRDAT0;
switch (length)
{
case NRF_QSPI_CINSTR_LEN_9B:
p_rx_data_8[7] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE7_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_8B:
p_rx_data_8[6] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE6_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_7B:
p_rx_data_8[5] = (uint8_t)(reg1 >> QSPI_CINSTRDAT1_BYTE5_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_6B:
p_rx_data_8[4] = (uint8_t)(reg1);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_5B:
p_rx_data_8[3] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE3_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_4B:
p_rx_data_8[2] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE2_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_3B:
p_rx_data_8[1] = (uint8_t)(reg0 >> QSPI_CINSTRDAT0_BYTE1_Pos);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_2B:
p_rx_data_8[0] = (uint8_t)(reg0);
/* fall-through */
case NRF_QSPI_CINSTR_LEN_1B:
/* Send only opcode. Case to avoid compiler warnings. */
break;
default:
break;
}
}
__STATIC_INLINE void nrf_qspi_cinstr_transfer_start(NRF_QSPI_Type * p_reg,
const nrf_qspi_cinstr_conf_t * p_config)
{
p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos));
}
__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_start(NRF_QSPI_Type * p_reg,
const nrf_qspi_cinstr_conf_t * p_config)
{
p_reg->CINSTRCONF = (((uint32_t)p_config->opcode << QSPI_CINSTRCONF_OPCODE_Pos) |
((uint32_t)p_config->length << QSPI_CINSTRCONF_LENGTH_Pos) |
((uint32_t)p_config->io2_level << QSPI_CINSTRCONF_LIO2_Pos) |
((uint32_t)p_config->io3_level << QSPI_CINSTRCONF_LIO3_Pos) |
((uint32_t)p_config->wipwait << QSPI_CINSTRCONF_WIPWAIT_Pos) |
((uint32_t)p_config->wren << QSPI_CINSTRCONF_WREN_Pos) |
(QSPI_CINSTRCONF_LFEN_Msk));
}
__STATIC_INLINE bool nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI_Type const * p_reg)
{
return (bool)((p_reg->CINSTRCONF & (QSPI_CINSTRCONF_LFEN_Msk | QSPI_CINSTRCONF_LFSTOP_Msk))
== QSPI_CINSTRCONF_LFEN_Msk);
}
__STATIC_INLINE void nrf_qspi_cinstr_long_transfer_continue(NRF_QSPI_Type * p_reg,
nrf_qspi_cinstr_len_t length,
bool finalize)
{
uint32_t mask = (((uint32_t)length << QSPI_CINSTRCONF_LENGTH_Pos) | (QSPI_CINSTRCONF_LFEN_Msk));
mask |= (finalize ? QSPI_CINSTRCONF_LFSTOP_Msk : 0);
p_reg->CINSTRCONF = mask;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_QSPI_H__

628
modules/nrfx/hal/nrf_spis.h
View File

@@ -1,628 +0,0 @@
/**
* Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_SPIS_H__
#define NRF_SPIS_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_spis_hal SPIS HAL
* @{
* @ingroup nrf_spis
* @brief Hardware access layer for managing the SPIS peripheral.
*/
/**
* @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
* function to specify that a given SPI signal (SCK, MOSI, or MISO)
* shall not be connected to a physical pin.
*/
#define NRF_SPIS_PIN_NOT_CONNECTED 0xFFFFFFFF
/** @brief SPIS tasks. */
typedef enum
{
NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
} nrf_spis_task_t;
/** @brief SPIS events. */
typedef enum
{
NRF_SPIS_EVENT_END = offsetof(NRF_SPIS_Type, EVENTS_END), ///< Granted transaction completed.
NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
} nrf_spis_event_t;
/** @brief SPIS shortcuts. */
typedef enum
{
NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task.
} nrf_spis_short_mask_t;
/** @brief SPIS interrupts. */
typedef enum
{
NRF_SPIS_INT_END_MASK = SPIS_INTENSET_END_Msk, ///< Interrupt on END event.
NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event.
} nrf_spis_int_mask_t;
/** @brief SPI modes. */
typedef enum
{
NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock.
NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock.
NRF_SPIS_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrf_spis_mode_t;
/** @brief SPI bit orders. */
typedef enum
{
NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
} nrf_spis_bit_order_t;
/** @brief SPI semaphore status. */
typedef enum
{
NRF_SPIS_SEMSTAT_FREE = 0, ///< Semaphore is free.
NRF_SPIS_SEMSTAT_CPU = 1, ///< Semaphore is assigned to the CPU.
NRF_SPIS_SEMSTAT_SPIS = 2, ///< Semaphore is assigned to the SPI slave.
NRF_SPIS_SEMSTAT_CPUPENDING = 3 ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
} nrf_spis_semstat_t;
/** @brief SPIS status. */
typedef enum
{
NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk ///< RX buffer overflow detected and prevented.
} nrf_spis_status_mask_t;
/**
* @brief Function for activating the specified SPIS task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
nrf_spis_task_t task);
/**
* @brief Function for getting the address of the specified SPIS task register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task The specified task.
*
* @return Address of the specified task register.
*/
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
nrf_spis_task_t task);
/**
* @brief Function for clearing the specified SPIS event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be cleared.
*/
__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event);
/**
* @brief Function for retrieving the state of the SPIS event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
nrf_spis_event_t event);
/**
* @brief Function for getting the address of the specified SPIS event register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event The specified event.
*
* @return Address of the specified event register.
*/
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
nrf_spis_event_t event);
/**
* @brief Function for enabling the specified shortcuts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
uint32_t mask);
/**
* @brief Function for disabling the specified shortcuts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
uint32_t mask);
/**
* @brief Function for enabling the specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
uint32_t mask);
/**
* @brief Function for disabling the specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] spis_int Interrupt to be checked.
*
* @retval true The interrupt is enabled.
* @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
nrf_spis_int_mask_t spis_int);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting the subscribe configuration for a given
* SPIS task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to set the configuration.
* @param[in] channel Channel through which to subscribe events.
*/
__STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,
nrf_spis_task_t task,
uint8_t channel);
/**
* @brief Function for clearing the subscribe configuration for a given
* SPIS task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to clear the configuration.
*/
__STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,
nrf_spis_task_t task);
/**
* @brief Function for setting the publish configuration for a given
* SPIS event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event for which to set the configuration.
* @param[in] channel Channel through which to publish the event.
*/
__STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event,
uint8_t channel);
/**
* @brief Function for clearing the publish configuration for a given
* SPIS event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event for which to clear the configuration.
*/
__STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event);
#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for enabling the SPIS peripheral.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg);
/**
* @brief Function for disabling the SPIS peripheral.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg);
/**
* @brief Function for retrieving the SPIS semaphore status.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Current semaphore status.
*/
__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg);
/**
* @brief Function for retrieving the SPIS status.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Current SPIS status.
*/
__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg);
/**
* @brief Function for configuring SPIS pins.
*
* If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] sck_pin SCK pin number.
* @param[in] mosi_pin MOSI pin number.
* @param[in] miso_pin MISO pin number.
* @param[in] csn_pin CSN pin number.
*/
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin,
uint32_t csn_pin);
/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the buffer that contains the data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t const * p_buffer,
size_t length);
/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buffer Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t * p_buffer,
size_t length);
/**
* @brief Function for getting the number of bytes transmitted
* in the last granted transaction.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Number of bytes transmitted.
*/
__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
/**
* @brief Function for getting the number of bytes received
* in the last granted transaction.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @returns Number of bytes received.
*/
__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
/**
* @brief Function for setting the SPI configuration.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] spi_mode SPI mode.
* @param[in] spi_bit_order SPI bit order.
*/
__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
nrf_spis_mode_t spi_mode,
nrf_spis_bit_order_t spi_bit_order);
/**
* @brief Function for setting the default character.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] def Default character that is clocked out in case of
* an overflow of the RXD buffer.
*/
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
uint8_t def);
/**
* @brief Function for setting the over-read character.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] orc Over-read character that is clocked out in case of
* an over-read of the TXD buffer.
*/
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
uint8_t orc);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_reg,
nrf_spis_task_t task)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_reg,
nrf_spis_task_t task)
{
return (uint32_t)p_reg + (uint32_t)task;
}
__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
nrf_spis_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_reg,
nrf_spis_event_t event)
{
return (uint32_t)p_reg + (uint32_t)event;
}
__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_reg,
uint32_t mask)
{
p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_reg,
uint32_t mask)
{
p_reg->SHORTS &= ~(mask);
}
__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_reg,
uint32_t mask)
{
p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_reg,
uint32_t mask)
{
p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_reg,
nrf_spis_int_mask_t spis_int)
{
return (bool)(p_reg->INTENSET & spis_int);
}
#if defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_spis_subscribe_set(NRF_SPIS_Type * p_reg,
nrf_spis_task_t task,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | SPIS_SUBSCRIBE_ACQUIRE_EN_Msk);
}
__STATIC_INLINE void nrf_spis_subscribe_clear(NRF_SPIS_Type * p_reg,
nrf_spis_task_t task)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
}
__STATIC_INLINE void nrf_spis_publish_set(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
((uint32_t)channel | SPIS_PUBLISH_END_EN_Msk);
}
__STATIC_INLINE void nrf_spis_publish_clear(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
}
#endif // defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_reg)
{
p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_reg)
{
p_reg->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_reg)
{
return (nrf_spis_semstat_t) ((p_reg->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk)
>> SPIS_SEMSTAT_SEMSTAT_Pos);
}
__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_reg)
{
return (nrf_spis_status_mask_t) p_reg->STATUS;
}
__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin,
uint32_t csn_pin)
{
#if defined (NRF51)
p_reg->PSELSCK = sck_pin;
p_reg->PSELMOSI = mosi_pin;
p_reg->PSELMISO = miso_pin;
p_reg->PSELCSN = csn_pin;
#else
p_reg->PSEL.SCK = sck_pin;
p_reg->PSEL.MOSI = mosi_pin;
p_reg->PSEL.MISO = miso_pin;
p_reg->PSEL.CSN = csn_pin;
#endif
}
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t const * p_buffer,
size_t length)
{
#if defined (NRF51)
p_reg->TXDPTR = (uint32_t)p_buffer;
p_reg->MAXTX = length;
#else
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
#endif
}
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t * p_buffer,
size_t length)
{
#if defined (NRF51)
p_reg->RXDPTR = (uint32_t)p_buffer;
p_reg->MAXRX = length;
#else
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;
#endif
}
__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)
{
#if defined (NRF51)
return p_reg->AMOUNTTX;
#else
return p_reg->TXD.AMOUNT;
#endif
}
__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
{
#if defined (NRF51)
return p_reg->AMOUNTRX;
#else
return p_reg->RXD.AMOUNT;
#endif
}
__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,
nrf_spis_mode_t spi_mode,
nrf_spis_bit_order_t spi_bit_order)
{
uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);
switch (spi_mode)
{
default:
case NRF_SPIS_MODE_0:
config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
break;
case NRF_SPIS_MODE_1:
config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
break;
case NRF_SPIS_MODE_2:
config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Leading << SPIS_CONFIG_CPHA_Pos);
break;
case NRF_SPIS_MODE_3:
config |= (SPIS_CONFIG_CPOL_ActiveLow << SPIS_CONFIG_CPOL_Pos) |
(SPIS_CONFIG_CPHA_Trailing << SPIS_CONFIG_CPHA_Pos);
break;
}
p_reg->CONFIG = config;
}
__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_reg,
uint8_t orc)
{
p_reg->ORC = orc;
}
__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_reg,
uint8_t def)
{
p_reg->DEF = def;
}
#endif // SUPPRESS_INLINE_IMPLEMENTATION
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_SPIS_H__

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@@ -1,189 +0,0 @@
/**
* Copyright (c) 2016 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_SYSTICK_H__
#define NRF_SYSTICK_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_systick_hal SYSTICK HAL
* @{
* @ingroup nrf_systick
* @brief Hardware access layer (HAL) for managing the SYSTICK peripheral.
*
* SYSTICK is a peripheral designed by ARM.
* This means that it does not feature the typical Nordic interface with Tasks and Events.
*
* Its usage is limited here to the implementation of simple delays.
* Moreover, keep in mind that this timer will be stopped when CPU is sleeping
* (WFE/WFI instruction is successfully executed).
*/
/**
* @brief Mask of usable bits in the SysTick value.
*/
#define NRF_SYSTICK_VAL_MASK SysTick_VAL_CURRENT_Msk
/**
* @brief Flags used by SysTick configuration.
*
* @sa nrf_systick_csr_set
* @sa nrf_systick_csr_get
*/
typedef enum {
NRF_SYSTICK_CSR_COUNTFLAG_MASK = SysTick_CTRL_COUNTFLAG_Msk, /**< Status flag: Returns 1 if timer counted to 0 since the last read of this register. */
NRF_SYSTICK_CSR_CLKSOURCE_MASK = SysTick_CTRL_CLKSOURCE_Msk, /**< Configuration bit: Select the SysTick clock source. */
NRF_SYSTICK_CSR_CLKSOURCE_REF = 0U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select reference clock. */
NRF_SYSTICK_CSR_CLKSOURCE_CPU = 1U << SysTick_CTRL_CLKSOURCE_Pos, /**< Configuration value: Select CPU clock. */
NRF_SYSTICK_CSR_TICKINT_MASK = SysTick_CTRL_TICKINT_Msk, /**< Configuration bit: Enables SysTick exception request. */
NRF_SYSTICK_CSR_TICKINT_ENABLE = 1U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero does not assert the SysTick exception request. */
NRF_SYSTICK_CSR_TICKINT_DISABLE = 0U << SysTick_CTRL_TICKINT_Pos, /**< Configuration value: Counting down to zero to asserts the SysTick exception request. */
NRF_SYSTICK_CSR_ENABLE_MASK = SysTick_CTRL_ENABLE_Msk, /**< Configuration bit: Enable the SysTick timer. */
NRF_SYSTICK_CSR_ENABLE = 1U << SysTick_CTRL_ENABLE_Pos, /**< Configuration value: Counter enabled. */
NRF_SYSTICK_CSR_DISABLE = 0U << SysTick_CTRL_ENABLE_Pos /**< Configuration value: Counter disabled. */
} nrf_systick_csr_flags_t;
/**
* @brief Function for getting Configuration and Status Register.
*
* @note The @ref NRF_SYSTICK_CSR_COUNTFLAG_MASK value is cleared when CSR register is read.
* @return Values composed by @ref nrf_systick_csr_flags_t.
*/
__STATIC_INLINE uint32_t nrf_systick_csr_get(void);
/**
* @brief Function for setting Configuration and Status Register.
*
* @param[in] val The value composed from @ref nrf_systick_csr_flags_t.
*/
__STATIC_INLINE void nrf_systick_csr_set(uint32_t val);
/**
* @brief Function for getting the current reload value.
*
* @return The reload register value.
*/
__STATIC_INLINE uint32_t nrf_systick_load_get(void);
/**
* @brief Function for configuring the reload value.
*
* @param[in] val The value to be set in the reload register.
*/
__STATIC_INLINE void nrf_systick_load_set(uint32_t val);
/**
* @brief Function for reading the SysTick current value.
*
* @return The current SysTick value
* @sa NRF_SYSTICK_VAL_MASK
*/
__STATIC_INLINE uint32_t nrf_systick_val_get(void);
/**
* @brief Function for clearing the SysTick current value.
*
* @note The SysTick does not allow setting current value.
* Any write to VAL register would clear the timer.
*/
__STATIC_INLINE void nrf_systick_val_clear(void);
/**
* @brief Function for reading the calibration register.
*
* @return The calibration register value.
*/
__STATIC_INLINE uint32_t nrf_systick_calib_get(void);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE uint32_t nrf_systick_csr_get(void)
{
return SysTick->CTRL;
}
__STATIC_INLINE void nrf_systick_csr_set(uint32_t val)
{
SysTick->CTRL = val;
}
__STATIC_INLINE uint32_t nrf_systick_load_get(void)
{
return SysTick->LOAD;
}
__STATIC_INLINE void nrf_systick_load_set(uint32_t val)
{
SysTick->LOAD = val;
}
__STATIC_INLINE uint32_t nrf_systick_val_get(void)
{
return SysTick->VAL;
}
__STATIC_INLINE void nrf_systick_val_clear(void)
{
SysTick->VAL = 0;
}
__STATIC_INLINE uint32_t nrf_systick_calib_get(void)
{
return SysTick->CALIB;
}
#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* NRF_SYSTICK_H__ */

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/**
* Copyright (c) 2012 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_TEMP_H__
#define NRF_TEMP_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_temp_hal_deprecated TEMP HAL (deprecated)
* @{
* @ingroup nrf_temp
* @brief Temperature module init and read functions.
*/
/** @brief Workaround specific define - sign mask.*/
#define MASK_SIGN (0x00000200UL)
/** @brief Workaround specific define - sign extension mask.*/
#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
/**
* @brief Function for preparing the TEMP module for temperature measurement.
*
* This function initializes the TEMP module and writes to the hidden configuration register.
*/
static __INLINE void nrf_temp_init(void)
{
/**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */
*(uint32_t *) 0x4000C504 = 0;
}
/**
* @brief Function for reading temperature measurement.
*
* The function reads the 10-bit 2's complement value and transforms it to a 32-bit 2's complement value.
*/
static __INLINE int32_t nrf_temp_read(void)
{
/**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */
return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ?
(int32_t)(NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);
}
/** @} */
/**
* @defgroup nrf_temp_hal TEMP HAL
* @{
* @ingroup nrf_temp
* @brief Hardware access layer for managing the Temperature sensor (TEMP).
*/
/** @brief TEMP tasks. */
typedef enum
{
NRF_TEMP_TASK_START = offsetof(NRF_TEMP_Type, TASKS_START), /**< Start temperature measurement. */
NRF_TEMP_TASK_STOP = offsetof(NRF_TEMP_Type, TASKS_STOP) /**< Stop temperature measurement. */
} nrf_temp_task_t;
/** @brief TEMP events. */
typedef enum
{
NRF_TEMP_EVENT_DATARDY = offsetof(NRF_TEMP_Type, EVENTS_DATARDY) /**< Temperature measurement complete, data ready. */
} nrf_temp_event_t;
/** @brief TEMP interrupts. */
typedef enum
{
NRF_TEMP_INT_DATARDY_MASK = TEMP_INTENSET_DATARDY_Msk /**< Interrupt on DATARDY event. */
} nrf_temp_int_mask_t;
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] temp_int Interrupt to be checked.
*
* @retval true The interrupt is enabled.
* @retval false The interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_temp_int_enable_check(NRF_TEMP_Type const * p_reg,
nrf_temp_int_mask_t temp_int);
/**
* @brief Function for getting the address of the specified TEMP task register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Requested task.
*
* @return Address of the requested task register.
*/
__STATIC_INLINE uint32_t nrf_temp_task_address_get(NRF_TEMP_Type const * p_reg,
nrf_temp_task_t task);
/**
* @brief Function for activating the specified TEMP task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t task);
/**
* @brief Function for getting the address of the specified TEMP event register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Requested event.
*
* @return Address of the requested event register.
*/
__STATIC_INLINE uint32_t nrf_temp_event_address_get(NRF_TEMP_Type const * p_reg,
nrf_temp_event_t event);
/**
* @brief Function for clearing the specified TEMP event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event);
/**
* @brief Function for getting the state of a specific event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_temp_event_check(NRF_TEMP_Type const * p_reg, nrf_temp_event_t event);
/**
* @brief Function for getting the result of temperature measurement.
*
* @note Returned value is in 2's complement format, 0.25 °C steps
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Temperature value register contents.
*/
__STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
}
__STATIC_INLINE void nrf_temp_int_disable(NRF_TEMP_Type * p_reg, uint32_t mask)
{
p_reg->INTENCLR = mask;
}
__STATIC_INLINE bool nrf_temp_int_enable_check(NRF_TEMP_Type const * p_reg,
nrf_temp_int_mask_t temp_int)
{
return (bool)(p_reg->INTENSET & temp_int);
}
__STATIC_INLINE uint32_t nrf_temp_task_address_get(NRF_TEMP_Type const * p_reg,
nrf_temp_task_t task)
{
return (uint32_t)((uint8_t *)p_reg + (uint32_t)task);
}
__STATIC_INLINE void nrf_temp_task_trigger(NRF_TEMP_Type * p_reg, nrf_temp_task_t task)
{
*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task) = 1;
}
__STATIC_INLINE uint32_t nrf_temp_event_address_get(NRF_TEMP_Type const * p_reg,
nrf_temp_event_t event)
{
return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
}
__STATIC_INLINE void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_temp_event_check(NRF_TEMP_Type const * p_reg, nrf_temp_event_t event)
{
return (bool)*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
}
__STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg)
{
int32_t raw_measurement = p_reg->TEMP;
#if defined(NRF51)
/* Apply workaround for the nRF51 series anomaly 28 - TEMP: Negative measured values are not represented correctly. */
if ((raw_measurement & 0x00000200) != 0)
{
raw_measurement |= 0xFFFFFC00UL;
}
#endif
return raw_measurement;
}
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif // NRF_TEMP_H__

745
modules/nrfx/hal/nrf_twis.h
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@@ -1,745 +0,0 @@
/**
* Copyright (c) 2015 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_TWIS_H__
#define NRF_TWIS_H__
#include <nrfx.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup nrf_twis_hal TWIS HAL
* @{
* @ingroup nrf_twis
* @brief Hardware access layer for managing the Two Wire Interface Slave with EasyDMA
* (TWIS) peripheral.
*/
/** @brief TWIS tasks. */
typedef enum
{
NRF_TWIS_TASK_STOP = offsetof(NRF_TWIS_Type, TASKS_STOP), /**< Stop TWIS transaction. */
NRF_TWIS_TASK_SUSPEND = offsetof(NRF_TWIS_Type, TASKS_SUSPEND), /**< Suspend TWIS transaction. */
NRF_TWIS_TASK_RESUME = offsetof(NRF_TWIS_Type, TASKS_RESUME), /**< Resume TWIS transaction. */
NRF_TWIS_TASK_PREPARERX = offsetof(NRF_TWIS_Type, TASKS_PREPARERX), /**< Prepare the TWIS slave to respond to a write command. */
NRF_TWIS_TASK_PREPARETX = offsetof(NRF_TWIS_Type, TASKS_PREPARETX) /**< Prepare the TWIS slave to respond to a read command. */
} nrf_twis_task_t;
/** @brief TWIS events. */
typedef enum
{
NRF_TWIS_EVENT_STOPPED = offsetof(NRF_TWIS_Type, EVENTS_STOPPED), /**< TWIS stopped. */
NRF_TWIS_EVENT_ERROR = offsetof(NRF_TWIS_Type, EVENTS_ERROR), /**< TWIS error. */
NRF_TWIS_EVENT_RXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_RXSTARTED), /**< Receive sequence started. */
NRF_TWIS_EVENT_TXSTARTED = offsetof(NRF_TWIS_Type, EVENTS_TXSTARTED), /**< Transmit sequence started. */
NRF_TWIS_EVENT_WRITE = offsetof(NRF_TWIS_Type, EVENTS_WRITE), /**< Write command received. */
NRF_TWIS_EVENT_READ = offsetof(NRF_TWIS_Type, EVENTS_READ) /**< Read command received. */
} nrf_twis_event_t;
/** @brief TWIS shortcuts. */
typedef enum
{
NRF_TWIS_SHORT_WRITE_SUSPEND_MASK = TWIS_SHORTS_WRITE_SUSPEND_Msk, /**< Shortcut between WRITE event and SUSPEND task. */
NRF_TWIS_SHORT_READ_SUSPEND_MASK = TWIS_SHORTS_READ_SUSPEND_Msk, /**< Shortcut between READ event and SUSPEND task. */
} nrf_twis_short_mask_t;
/** @brief TWIS interrupts. */
typedef enum
{
NRF_TWIS_INT_STOPPED_MASK = TWIS_INTEN_STOPPED_Msk, /**< Interrupt on STOPPED event. */
NRF_TWIS_INT_ERROR_MASK = TWIS_INTEN_ERROR_Msk, /**< Interrupt on ERROR event. */
NRF_TWIS_INT_RXSTARTED_MASK = TWIS_INTEN_RXSTARTED_Msk, /**< Interrupt on RXSTARTED event. */
NRF_TWIS_INT_TXSTARTED_MASK = TWIS_INTEN_TXSTARTED_Msk, /**< Interrupt on TXSTARTED event. */
NRF_TWIS_INT_WRITE_MASK = TWIS_INTEN_WRITE_Msk, /**< Interrupt on WRITE event. */
NRF_TWIS_INT_READ_MASK = TWIS_INTEN_READ_Msk, /**< Interrupt on READ event. */
} nrf_twis_int_mask_t;
/** @brief TWIS error source. */
typedef enum
{
NRF_TWIS_ERROR_OVERFLOW = TWIS_ERRORSRC_OVERFLOW_Msk, /**< RX buffer overflow detected, and prevented. */
NRF_TWIS_ERROR_DATA_NACK = TWIS_ERRORSRC_DNACK_Msk, /**< NACK sent after receiving a data byte. */
NRF_TWIS_ERROR_OVERREAD = TWIS_ERRORSRC_OVERREAD_Msk /**< TX buffer over-read detected, and prevented. */
} nrf_twis_error_t;
/** @brief TWIS address matching configuration. */
typedef enum
{
NRF_TWIS_CONFIG_ADDRESS0_MASK = TWIS_CONFIG_ADDRESS0_Msk, /**< Enable or disable address matching on ADDRESS[0]. */
NRF_TWIS_CONFIG_ADDRESS1_MASK = TWIS_CONFIG_ADDRESS1_Msk, /**< Enable or disable address matching on ADDRESS[1]. */
NRF_TWIS_CONFIG_ADDRESS01_MASK = TWIS_CONFIG_ADDRESS0_Msk | TWIS_CONFIG_ADDRESS1_Msk /**< Enable both address matching. */
} nrf_twis_config_addr_mask_t;
/**
* @brief Variable type to hold the amount of data for EasyDMA.
*
* Variable of the minimum size that can hold the amount of data to transfer.
*
* @note Defined to make it simple to change if EasyDMA is updated to support more data in
* the future devices.
*/
typedef uint8_t nrf_twis_amount_t;
/**
* @brief Smallest variable type to hold the TWI address.
*
* Variable of the minimum size that can hold a single TWI address.
*
* @note Defined to make it simple to change if the new TWI supports for example
* 10 bit addressing mode.
*/
typedef uint8_t nrf_twis_address_t;
/**
* @brief Function for activating the specified TWIS task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task to be activated.
*/
__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task);
/**
* @brief Function for returning the address of the specified TWIS task register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task The specified task.
*
* @return Task address.
*/
__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg,
nrf_twis_task_t task);
/**
* @brief Function for clearing the specified event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event The specified event.
*/
__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg,
nrf_twis_event_t event);
/**
* @brief Function for retrieving the state of the TWIS event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event to be checked.
*
* @retval true The event has been generated.
* @retval false The event has not been generated.
*/
__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg,
nrf_twis_event_t event);
/**
* @brief Function for getting and clearing the state of the specified event.
*
* This function checks the state of the event and clears it.
*
* @param[in,out] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event.
*
* @retval true The event was set.
* @retval false The event was not set.
*/
__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg,
nrf_twis_event_t event);
/**
* @brief Function for returning the address of the specified TWIS event register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event.
*
* @return Address.
*/
__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg,
nrf_twis_event_t event);
/**
* @brief Function for setting a shortcut.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of shortcuts to be enabled.
*/
__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask);
/**
* @brief Function for clearing shortcuts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of shortcuts to be disabled.
*/
__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask);
/**
* @brief Function for getting the shorts mask.
*
* Function returns shorts register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Flags of currently enabled shortcuts
*/
__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg);
/**
* @brief Function for enabling the specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be enabled.
*/
__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask);
/**
* @brief Function for retrieving the state of the specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be checked.
*
* @retval true Any of the specified interrupts is enabled.
* @retval false None of the specified interrupts is enabled.
*/
__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask);
/**
* @brief Function for disabling the specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] mask Mask of interrupts to be disabled.
*/
__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * p_reg, uint32_t mask);
#if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting the subscribe configuration for a given
* TWIS task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to set the configuration.
* @param[in] channel Channel through which to subscribe events.
*/
__STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg,
nrf_twis_task_t task,
uint8_t channel);
/**
* @brief Function for clearing the subscribe configuration for a given
* TWIS task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] task Task for which to clear the configuration.
*/
__STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg,
nrf_twis_task_t task);
/**
* @brief Function for setting the publish configuration for a given
* TWIS event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event for which to set the configuration.
* @param[in] channel Channel through which to publish the event.
*/
__STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg,
nrf_twis_event_t event,
uint8_t channel);
/**
* @brief Function for clearing the publish configuration for a given
* TWIS event.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] event Event for which to clear the configuration.
*/
__STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg,
nrf_twis_event_t event);
#endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for retrieving and clearing the TWIS error source.
*
* @attention Error sources are cleared after read.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Error source mask with values from @ref nrf_twis_error_t.
*/
__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * const p_reg);
/**
* @brief Function for getting information about which of the addresses matched.
*
* Function returns index in the address table
* that points to the address that already matched.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Index of matched address.
*/
__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg);
/**
* @brief Function for enabling TWIS.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg);
/**
* @brief Function for disabling TWIS.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*/
__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg);
/**
* @brief Function for configuring TWIS pins.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] scl SCL pin number.
* @param[in] sda SDA pin number.
*/
__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda);
/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buf Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg,
uint8_t * p_buf,
size_t length);
/**
* @brief Function that prepares TWIS for receiving
*
* This function sets receive buffer and then sets NRF_TWIS_TASK_PREPARERX task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buf Pointer to the buffer for received data.
* @param[in] length Maximum number of data bytes to receive.
*/
__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg,
uint8_t * p_buf,
size_t length);
/**
* @brief Function for getting number of bytes received in the last transaction.
*
* @param[in] p_reg TWIS instance.
*
* @return Amount of bytes received.
* */
__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg);
/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buf Pointer to the buffer with data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg,
uint8_t const * p_buf,
size_t length);
/**
* @brief Function for preparing TWIS for transmitting.
*
* This function sets transmit buffer and then sets NRF_TWIS_TASK_PREPARETX task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] p_buf Pointer to the buffer with data to send.
* @param[in] length Maximum number of data bytes to transmit.
*/
__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg,
uint8_t const * p_buf,
size_t length);
/**
* @brief Function for getting the number of bytes transmitted in the last transaction.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Amount of bytes transmitted.
*/
__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg);
/**
* @brief Function for setting the slave address.
*
* Function sets the selected address for this TWI interface.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] n Index of address to be set.
* @param[in] addr Addres to be set.
*
* @sa nrf_twis_config_address_set
* @sa nrf_twis_config_address_get
*/
__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg,
uint_fast8_t n,
nrf_twis_address_t addr);
/**
* @brief Function for retrieving configured slave address.
*
* Function gets the selected address for this TWI interface.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] n Index of address to get.
*
* @return Configured slave address.
*/
__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg,
uint_fast8_t n);
/**
* @brief Function for setting the device address configuration.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] addr_mask Mask of address indexes of what device should answer to.
*
* @sa nrf_twis_address_set
*/
__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg,
nrf_twis_config_addr_mask_t addr_mask);
/**
* @brief Function for retrieving the device address configuration.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Mask of address indexes of what device should answer to.
*/
__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(
NRF_TWIS_Type const * p_reg);
/**
* @brief Function for setting the over-read character.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] orc Over-read character. Character clocked out in case of
* over-read of the TXD buffer.
*/
__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg,
uint8_t orc);
/**
* @brief Function for setting the over-read character.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
* @return Over-read character configured for selected instance.
*/
__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg);
/** @} */ /* End of nrf_twis_hal */
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
/* ------------------------------------------------------------------------------------------------
* Internal functions
*/
/**
* @internal
* @brief Internal function for getting task or event register address.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] offset Offset of the register from the beginning of the instance.
*
* @attention Offset must be modulo 4 value. In other case, hardware fault can occur.
* @return Pointer to the register.
*/
__STATIC_INLINE volatile uint32_t* nrf_twis_getRegPtr(NRF_TWIS_Type const * p_reg, uint32_t offset)
{
return (volatile uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
}
/**
* @internal
* @brief Internal function for getting task/event register address - constant version.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] offset Offset of the register from the beginning of the instance.
*
* @attention Offset must be modulo 4 value. In other case, hardware fault can occur.
* @return Pointer to the register.
*/
__STATIC_INLINE volatile const uint32_t* nrf_twis_getRegPtr_c(NRF_TWIS_Type const * p_reg,
uint32_t offset)
{
return (volatile const uint32_t*)((uint8_t *)p_reg + (uint32_t)offset);
}
/* ------------------------------------------------------------------------------------------------
* Interface functions definitions
*/
__STATIC_INLINE void nrf_twis_task_trigger(NRF_TWIS_Type * p_reg, nrf_twis_task_t task)
{
*(nrf_twis_getRegPtr(p_reg, (uint32_t)task)) = 1UL;
}
__STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg,
nrf_twis_task_t task)
{
return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)task);
}
__STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event)
{
*(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL;
#if __CORTEX_M == 0x04
volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
(void)dummy;
#endif
}
__STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, nrf_twis_event_t event)
{
return (bool)*nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
}
__STATIC_INLINE bool nrf_twis_event_get_and_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event)
{
bool ret = nrf_twis_event_check(p_reg, event);
if (ret)
{
nrf_twis_event_clear(p_reg, event);
}
return ret;
}
__STATIC_INLINE uint32_t nrf_twis_event_address_get(NRF_TWIS_Type const * p_reg,
nrf_twis_event_t event)
{
return (uint32_t)nrf_twis_getRegPtr_c(p_reg, (uint32_t)event);
}
__STATIC_INLINE void nrf_twis_shorts_enable(NRF_TWIS_Type * p_reg, uint32_t mask)
{
p_reg->SHORTS |= mask;
}
__STATIC_INLINE void nrf_twis_shorts_disable(NRF_TWIS_Type * p_reg, uint32_t mask)
{
if (~0U == mask)
{
/* Optimized version for "disable all" */
p_reg->SHORTS = 0;
}
else
{
p_reg->SHORTS &= ~mask;
}
}
__STATIC_INLINE uint32_t nrf_twis_shorts_get(NRF_TWIS_Type const * p_reg)
{
return p_reg->SHORTS;
}
__STATIC_INLINE void nrf_twis_int_enable(NRF_TWIS_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
}
__STATIC_INLINE bool nrf_twis_int_enable_check(NRF_TWIS_Type const * p_reg, uint32_t mask)
{
return (bool)(p_reg->INTENSET & mask);
}
__STATIC_INLINE void nrf_twis_int_disable(NRF_TWIS_Type * const p_reg, uint32_t mask)
{
p_reg->INTENCLR = mask;
}
#if defined(DPPI_PRESENT)
__STATIC_INLINE void nrf_twis_subscribe_set(NRF_TWIS_Type * p_reg,
nrf_twis_task_t task,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
((uint32_t)channel | TWIS_SUBSCRIBE_STOP_EN_Msk);
}
__STATIC_INLINE void nrf_twis_subscribe_clear(NRF_TWIS_Type * p_reg,
nrf_twis_task_t task)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
}
__STATIC_INLINE void nrf_twis_publish_set(NRF_TWIS_Type * p_reg,
nrf_twis_event_t event,
uint8_t channel)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
((uint32_t)channel | TWIS_PUBLISH_STOPPED_EN_Msk);
}
__STATIC_INLINE void nrf_twis_publish_clear(NRF_TWIS_Type * p_reg,
nrf_twis_event_t event)
{
*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
}
#endif // defined(DPPI_PRESENT)
__STATIC_INLINE uint32_t nrf_twis_error_source_get_and_clear(NRF_TWIS_Type * p_reg)
{
uint32_t ret = p_reg->ERRORSRC;
p_reg->ERRORSRC = ret;
return ret;
}
__STATIC_INLINE uint_fast8_t nrf_twis_match_get(NRF_TWIS_Type const * p_reg)
{
return (uint_fast8_t)p_reg->MATCH;
}
__STATIC_INLINE void nrf_twis_enable(NRF_TWIS_Type * p_reg)
{
p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Enabled << TWIS_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg)
{
p_reg->ENABLE = (TWIS_ENABLE_ENABLE_Disabled << TWIS_ENABLE_ENABLE_Pos);
}
__STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda)
{
p_reg->PSEL.SCL = scl;
p_reg->PSEL.SDA = sda;
}
__STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg,
uint8_t * p_buf,
size_t length)
{
p_reg->RXD.PTR = (uint32_t)p_buf;
p_reg->RXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_twis_rx_prepare(NRF_TWIS_Type * p_reg,
uint8_t * p_buf,
size_t length)
{
nrf_twis_rx_buffer_set(p_reg, p_buf, length);
nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARERX);
}
__STATIC_INLINE size_t nrf_twis_rx_amount_get(NRF_TWIS_Type const * p_reg)
{
return p_reg->RXD.AMOUNT;
}
__STATIC_INLINE void nrf_twis_tx_buffer_set(NRF_TWIS_Type * p_reg,
uint8_t const * p_buf,
size_t length)
{
p_reg->TXD.PTR = (uint32_t)p_buf;
p_reg->TXD.MAXCNT = length;
}
__STATIC_INLINE void nrf_twis_tx_prepare(NRF_TWIS_Type * p_reg,
uint8_t const * p_buf,
size_t length)
{
nrf_twis_tx_buffer_set(p_reg, p_buf, length);
nrf_twis_task_trigger(p_reg, NRF_TWIS_TASK_PREPARETX);
}
__STATIC_INLINE size_t nrf_twis_tx_amount_get(NRF_TWIS_Type const * p_reg)
{
return p_reg->TXD.AMOUNT;
}
__STATIC_INLINE void nrf_twis_address_set(NRF_TWIS_Type * p_reg,
uint_fast8_t n,
nrf_twis_address_t addr)
{
p_reg->ADDRESS[n] = addr;
}
__STATIC_INLINE nrf_twis_address_t nrf_twis_address_get(NRF_TWIS_Type const * p_reg, uint_fast8_t n)
{
return (nrf_twis_address_t)p_reg->ADDRESS[n];
}
__STATIC_INLINE void nrf_twis_config_address_set(NRF_TWIS_Type * p_reg,
nrf_twis_config_addr_mask_t addr_mask)
{
/* This is the only configuration in TWIS - just write it without masking */
p_reg->CONFIG = addr_mask;
}
__STATIC_INLINE nrf_twis_config_addr_mask_t nrf_twis_config_address_get(NRF_TWIS_Type const * p_reg)
{
return (nrf_twis_config_addr_mask_t)(p_reg->CONFIG & TWIS_ADDRESS_ADDRESS_Msk);
}
__STATIC_INLINE void nrf_twis_orc_set(NRF_TWIS_Type * p_reg, uint8_t orc)
{
p_reg->ORC = orc;
}
__STATIC_INLINE uint8_t nrf_twis_orc_get(NRF_TWIS_Type const * p_reg)
{
return (uint8_t)p_reg->ORC;
}
#endif /* SUPPRESS_INLINE_IMPLEMENTATION */
#ifdef __cplusplus
}
#endif
#endif /* NRF_TWIS_H__ */

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