jh.chun/VesiScan-Basic_imu
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

기타

Browse Source
This commit is contained in:
jhchun
2026-04-30 12:26:09 +09:00
parent 7bc8bbd178
commit 216fe63b44
5 changed files with 63 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files
project/ble_peripheral/ble_app_bladder_patch/measurement/adc121s051/dr_adc121s051.c
+1 -17
View File
@@ -83,6 +83,7 @@ extern void dr_piezo_power_off(void);
#define BLE_REB_DATA_LEN (BLE_MTU_SIZE - BLE_REB_HEADER_LEN) /* 238 bytes = 119 samples */
#define BLE_RED_DATA_LEN (BLE_MTU_SIZE - BLE_RED_HEADER_LEN) /* 238 bytes = 119 samples */
#define BLE_PACKET_DELAY_MS 100 /* Inter-packet delay - allow BLE TX buffer to drain */
#define DR_ADC_AVG_INTER_BURST_GAP_US 500 /* Gap between averaged bursts to reduce residual echo carry-over */
/* Piezo MUX pins (8ch) */
#define DR_PIEZO_EN_MUXA NRF_GPIO_PIN_MAP(0, 21) /**< MUXA Enable */
@@ -548,24 +549,7 @@ extern void dr_piezo_burst_sw(uint8_t cycles);
/*==============================================================================
* PIEZO CHANNEL SELECTION
*============================================================================*/
/*
* Channel mapping (8ch)
* | EN MUXA | EN MUXB | SEL 0 | SEL 1
* ----------------------------------------------
* CH A0 | 1 | 0 | 0 | 0
* CH A1 | 1 | 0 | 0 | 1
* CH A2 | 1 | 0 | 1 | 0
* CH A3 | 1 | 0 | 1 | 1
* ----------------------------------------------
* CH B3 | 0 | 1 | 0 | 0
* CH B2 | 0 | 1 | 0 | 1
* CH B1 | 0 | 1 | 1 | 0
* CH B0 | 0 | 1 | 1 | 1
*/
/* dr_piezo_select_channel is defined in dr_piezo.c */
extern void dr_piezo_select_channel(uint8_t channel);
/* Channel selection is split into GPIO switch and timer-backed settling wait. */
extern void dr_piezo_select_channel_start(uint8_t channel);
extern void dr_piezo_wait_mux_settled(void);
project/ble_peripheral/ble_app_bladder_patch/measurement/piezo/dr_piezo.c
+5 -14
View File
@@ -681,22 +681,14 @@ void dr_piezo_select_channel_start(uint8_t channel)
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXB); nrf_gpio_pin_set(DR_PIEZO_EN_MUXA);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
break;
/*case 4: // B0: EN_MUXA=0, EN_MUXB=1, SEL0=1, SEL1=1
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
break;
case 5: // B1: EN_MUXA=0, EN_MUXB=1, SEL0=0, SEL1=1
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_set(DR_PIEZO_MUX_SEL1);
break;*/
case 5: // B2: EN_MUXA=0, EN_MUXB=1, SEL0=1, SEL1=0
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
break;
case 4: // B3: EN_MUXA=0, EN_MUXB=1, SEL0=0, SEL1=0
case 4: // B0: EN_MUXA=0, EN_MUXB=1, SEL0=0, SEL1=0
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
break;
case 5: // B1: EN_MUXA=0, EN_MUXB=1, SEL0=1, SEL1=0
nrf_gpio_pin_clear(DR_PIEZO_EN_MUXA); nrf_gpio_pin_set(DR_PIEZO_EN_MUXB);
nrf_gpio_pin_set(DR_PIEZO_MUX_SEL0); nrf_gpio_pin_clear(DR_PIEZO_MUX_SEL1);
break;
}
/* Start one-shot timer for MUX settling (> 1.2ms). */
@@ -1621,4 +1613,3 @@ void dr_piezo_burst_sw_17mhz(uint8_t cycles)
__enable_irq();
}