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jhChun
2026-04-08 16:58:54 +09:00
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12
project/dfu/private_key.c Normal file
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/* This file was automatically generated by nrfutil on 2022-09-06 (YY-MM-DD) at 15:11:25 */
#include "stdint.h"
#include "compiler_abstraction.h"
/** @brief Public key used to verify DFU images */
__ALIGN(4) const uint8_t pk[64] =
{
0x67, 0x5b, 0xcb, 0x03, 0xe5, 0x70, 0x6a, 0x83, 0x6c, 0x5e, 0x17, 0xbc, 0x81, 0x20, 0x27, 0xdc, 0x76, 0x6b, 0xae, 0x9b, 0x89, 0x72, 0x1a, 0x28, 0x31, 0x2a, 0x9b, 0x35, 0xbe, 0x1a, 0x90, 0xd5,
0xec, 0x4b, 0x24, 0x39, 0xb5, 0x79, 0x5f, 0x5a, 0xd7, 0x3b, 0xd8, 0x86, 0xa7, 0x80, 0xa9, 0x2d, 0xc4, 0xf6, 0xd6, 0x03, 0xa0, 0xe6, 0xd8, 0xc7, 0x03, 0x3e, 0x28, 0xe2, 0x76, 0x08, 0x88, 0xfa
};

121
project/dfu/secure_bootloader/main.c Normal file
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/*******************************************************************************
* @file main.c
* @author CandyPops Co.
* @version V1.0.0
* @date 2022-09-05
* @brief
******************************************************************************/
#include <stdint.h>
#include "boards.h"
#include "nrf_mbr.h"
#include "nrf_bootloader.h"
#include "nrf_bootloader_app_start.h"
#include "nrf_bootloader_dfu_timers.h"
#include "nrf_dfu.h"
#include "nrf_log.h"
#include "nrf_log_ctrl.h"
#include "nrf_log_default_backends.h"
#include "app_error.h"
#include "app_error_weak.h"
#include "nrf_bootloader_info.h"
#include "nrf_delay.h"
#define POWER_HOLD NRF_GPIO_PIN_MAP(0,8) // power hold port for medithings device
static void on_error(void)
{
NRF_LOG_FINAL_FLUSH();
#if NRF_MODULE_ENABLED(NRF_LOG_BACKEND_RTT)
// To allow the buffer to be flushed by the host.
nrf_delay_ms(100);
#endif
#ifdef NRF_DFU_DEBUG_VERSION
NRF_BREAKPOINT_COND;
#endif
NVIC_SystemReset();
}
void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name)
{
NRF_LOG_ERROR("%s:%d", p_file_name, line_num);
on_error();
}
void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info)
{
NRF_LOG_ERROR("Received a fault! id: 0x%08x, pc: 0x%08x, info: 0x%08x", id, pc, info);
on_error();
}
void app_error_handler_bare(uint32_t error_code)
{
NRF_LOG_ERROR("Received an error: 0x%08x!", error_code);
on_error();
}
/**
* @brief Function notifies certain events in DFU process.
*/
static void dfu_observer(nrf_dfu_evt_type_t evt_type)
{
switch (evt_type)
{
case NRF_DFU_EVT_DFU_FAILED:
case NRF_DFU_EVT_DFU_ABORTED:
case NRF_DFU_EVT_DFU_INITIALIZED:
bsp_board_init(BSP_INIT_LEDS);
bsp_board_led_on(BSP_BOARD_LED_0);
break;
case NRF_DFU_EVT_TRANSPORT_ACTIVATED:
bsp_board_led_on(BSP_BOARD_LED_0);
break;
case NRF_DFU_EVT_DFU_STARTED:
break;
default:
break;
}
}
/**@brief Function for application main entry. */
int main(void)
{
uint32_t ret_val;
nrf_gpio_cfg_output(POWER_HOLD);
nrf_gpio_pin_set(POWER_HOLD); // The medithings device performs power hold when the power button is pressed for 3 seconds.
// And then, The medithings device loads the bootloader.
// Must happen before flash protection is applied, since it edits a protected page.
nrf_bootloader_mbr_addrs_populate();
// Protect MBR and bootloader code from being overwritten.
ret_val = nrf_bootloader_flash_protect(0, MBR_SIZE);
APP_ERROR_CHECK(ret_val);
ret_val = nrf_bootloader_flash_protect(BOOTLOADER_START_ADDR, BOOTLOADER_SIZE);
APP_ERROR_CHECK(ret_val);
(void) NRF_LOG_INIT(nrf_bootloader_dfu_timer_counter_get);
NRF_LOG_DEFAULT_BACKENDS_INIT();
NRF_LOG_INFO("Inside main");
ret_val = nrf_bootloader_init(dfu_observer);
APP_ERROR_CHECK(ret_val);
NRF_LOG_FLUSH();
NRF_LOG_ERROR("After main, should never be reached.");
NRF_LOG_FLUSH();
APP_ERROR_CHECK_BOOL(false);
}
/**
* @}
*/

58
project/dfu/secure_bootloader/nrf_crypto_allocator.h Normal file
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/**
* Copyright (c) 2019 - 2021, Nordic Semiconductor ASA
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic
* Semiconductor ASA integrated circuit in a product or a software update for
* such product, must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_CRYPTO_ALLOCATOR_H__
#define NRF_CRYPTO_ALLOCATOR_H__
#include "nrf_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Crypto library in bootloader case does not use dynamic allocation */
#define NRF_CRYPTO_ALLOC(size) NULL; ASSERT(0)
#define NRF_CRYPTO_ALLOC_ON_STACK(size) NULL; ASSERT(0)
#define NRF_CRYPTO_FREE(ptr) (void)ptr;
#ifdef __cplusplus
}
#endif
#endif /* NRF_CRYPTO_ALLOCATOR_H__ */

103
project/dfu/secure_bootloader/pca10056_s140_ble/arm5_no_packs/JLinkLog.txt Normal file
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TDF48 000:201.240 SEGGER J-Link V9.16 Log File
TDF48 000:201.384 DLL Compiled: Feb 4 2026 12:52:08
TDF48 000:201.390 Logging started @ 2026-04-08 05:51
TDF48 000:201.395 Process: C:\Keil_v5\UV4\UV4.exe
TDF48 000:201.409 - 201.399ms
TDF48 000:201.417 JLINK_SetWarnOutHandler(...)
TDF48 000:201.422 - 0.006ms
TDF48 000:201.432 JLINK_OpenEx(...)
TDF48 000:209.460 Firmware: J-Link OB-SAM3U128-V2-NordicSemi compiled Jul 8 2025 10:14:41
TDF48 000:210.198 Firmware: J-Link OB-SAM3U128-V2-NordicSemi compiled Jul 8 2025 10:14:41
TDF48 000:228.689 Hardware: V1.00
TDF48 000:228.730 S/N: 682811713
TDF48 000:228.739 OEM: SEGGER
TDF48 000:228.748 Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
TDF48 000:229.654 Bootloader: 2014 Sep 11
TDF48 000:246.394 USB speed mode: High speed (480 MBit/s)
TDF48 000:247.130 TELNET listener socket opened on port 19021
TDF48 000:247.502 WEBSRV WEBSRV_Init(): Starting webserver thread(s)
TDF48 000:247.738 WEBSRV Failed to put socket into listener state (port 19080)
TDF48 000:247.915 WEBSRV Webserver running on local port 19081
TDF48 000:248.062 Looking for J-Link GUI Server exe at: C:\Keil_v5\ARM\Segger\JLinkGUIServer.exe
TDF48 000:248.156 Looking for J-Link GUI Server exe at: C:\Program Files\SEGGER\JLink_V916\JLinkGUIServer.exe
TDF48 000:248.204 Forking J-Link GUI Server: C:\Program Files\SEGGER\JLink_V916\JLinkGUIServer.exe
TDF48 000:253.313 J-Link GUI Server info: "J-Link GUI server V8.98 "
TDF48 000:253.807 - 52.355ms returns "O.K."
TDF48 000:253.879 JLINK_GetEmuCaps()
TDF48 000:253.900 - 0.016ms returns 0xB8EA5A33
TDF48 000:253.908 JLINK_TIF_GetAvailable(...)
TDF48 000:254.498 - 0.589ms
TDF48 000:254.543 JLINK_SetErrorOutHandler(...)
TDF48 000:254.550 - 0.006ms
TDF48 000:254.582 JLINK_ExecCommand("ProjectFile = "C:\jhChun\vivamyo\project\dfu\secure_bootloader\pca10056_s140_ble\arm5_no_packs\JLinkSettings.ini"", ...).
TDF48 000:269.693 Ref file found at: C:\Keil_v5\ARM\Segger\JLinkDevices.ref
TDF48 000:269.778 REF file references invalid XML file: C:\Program Files\SEGGER\JLink_V916\JLinkDevices.xml
TDF48 000:271.124 - 16.543ms returns 0x00
TDF48 000:271.153 JLINK_ExecCommand("Device = nRF52840_xxAA", ...).
TDF48 000:271.295 Flash bank @ 0x00000000: SFL: Parsing sectorization info from ELF file
TDF48 000:271.306 FlashDevice.SectorInfo[0]: .SectorSize = 0x00000400, .SectorStartAddr = 0x00000000
TDF48 000:271.314 FlashBank @0x00000000: Sectorization info from SFL ELF file ignored because sectorization override from DLL / XML file is active.
TDF48 000:271.758 Flash bank @ 0x12000000: SFL: Parsing sectorization info from ELF file
TDF48 000:271.768 FlashDevice.SectorInfo[0]: .SectorSize = 0x00010000, .SectorStartAddr = 0x00000000
TDF48 000:276.246 Device "NRF52840_XXAA" selected.
TDF48 000:276.553 - 5.399ms returns 0x00
TDF48 000:276.577 ERROR: Unknown command
TDF48 000:276.590 JLINK_GetHardwareVersion()
TDF48 000:276.596 - 0.005ms returns 10000
TDF48 000:276.602 JLINK_GetDLLVersion()
TDF48 000:276.606 - 0.004ms returns 91600
TDF48 000:276.612 JLINK_GetOEMString(...)
TDF48 000:276.619 JLINK_GetFirmwareString(...)
TDF48 000:276.624 - 0.005ms
TDF48 000:276.633 JLINK_GetDLLVersion()
TDF48 000:276.637 - 0.004ms returns 91600
TDF48 000:276.642 JLINK_GetCompileDateTime()
TDF48 000:276.647 - 0.004ms
TDF48 000:276.655 JLINK_GetFirmwareString(...)
TDF48 000:276.659 - 0.004ms
TDF48 000:276.665 JLINK_GetHardwareVersion()
TDF48 000:276.670 - 0.004ms returns 10000
TDF48 000:276.676 JLINK_GetSN()
TDF48 000:276.681 - 0.004ms returns 682811713
TDF48 000:276.687 JLINK_GetOEMString(...)
TDF48 000:276.694 JLINK_TIF_Select(JLINKARM_TIF_SWD)
TDF48 000:277.908 - 1.213ms returns 0x00
TDF48 000:277.983 JLINK_HasError()
TDF48 000:278.004 JLINK_SetSpeed(5000)
TDF48 000:278.243 - 0.240ms
TDF48 000:278.669 JLINK_HasError()
TDF48 000:278.685 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL)
TDF48 000:278.691 - 0.006ms returns JLINKARM_RESET_TYPE_NORMAL
TDF48 000:278.708 JLINK_Reset()
TDF48 000:279.183 InitTarget() start
TDF48 000:279.261 J-Link Script File: Executing InitTarget()
TDF48 000:389.055 InitTarget() end - Took 109ms
TDF48 000:495.039 Connect fallback: Reset via Reset pin & Connect.
TDF48 000:551.269 InitTarget() start
TDF48 000:551.299 J-Link Script File: Executing InitTarget()
TDF48 000:661.077 InitTarget() end - Took 109ms
TDF48 000:766.189 - 487.476ms
TDF48 000:766.524 JLINK_GetId()
TDF48 000:767.060 InitTarget() start
TDF48 000:767.086 J-Link Script File: Executing InitTarget()
TDF48 000:876.594 InitTarget() end - Took 109ms
TDF48 000:981.144 Connect fallback: Reset via Reset pin & Connect.
TDF48 001:038.861 InitTarget() start
TDF48 001:038.994 J-Link Script File: Executing InitTarget()
TDF48 001:148.249 InitTarget() end - Took 109ms
TDF48 001:253.999 - 487.473ms returns 0x00000000
TDF48 001:254.198 JLINK_GetId()
TDF48 001:254.682 InitTarget() start
TDF48 001:254.704 J-Link Script File: Executing InitTarget()
TDF48 001:363.500 InitTarget() end - Took 108ms
TDF48 001:467.558 Connect fallback: Reset via Reset pin & Connect.
TDF48 001:524.692 InitTarget() start
TDF48 001:524.788 J-Link Script File: Executing InitTarget()
TDF48 001:633.966 InitTarget() end - Took 109ms
TDF48 001:739.196 - 484.994ms returns 0x00000000
TDF48 001:746.741 JLINK_GetFirmwareString(...)
TDF48 001:746.775 - 0.033ms
TDF48 004:866.607 JLINK_Close()
TDF48 004:868.432 - 1.824ms
TDF48 004:868.448
TDF48 004:868.453 Closed

45
project/dfu/secure_bootloader/pca10056_s140_ble/arm5_no_packs/JLinkSettings.ini Normal file
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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
RMWThreshold = 0x400
Loaders=""
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
MaxNumTransfers = 0x00
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
[RAM]
VerifyDownload = 0x00
[DYN_MEM_MAP]
NumUserRegion = 0x00

383
project/dfu/secure_bootloader/pca10056_s140_ble/arm5_no_packs/RTE/Device/nRF52840_xxAA/arm_startup_nrf52840.s Normal file
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; Copyright (c) 2009-2021 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
; Licensed under the Apache License, Version 2.0 (the License); you may
; not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
IF :DEF: __STARTUP_CONFIG
#ifdef __STARTUP_CONFIG
#include "startup_config.h"
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
#endif
#endif
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 16384
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
ELSE
Stack_Align EQU 3
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
Stack_Mem SPACE Stack_Size
__initial_sp
IF :DEF: __STARTUP_CONFIG
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 16384
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0 ; Reserved
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD NFCT_IRQHandler
DCD GPIOTE_IRQHandler
DCD SAADC_IRQHandler
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
DCD RTC0_IRQHandler
DCD TEMP_IRQHandler
DCD RNG_IRQHandler
DCD ECB_IRQHandler
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
DCD QDEC_IRQHandler
DCD COMP_LPCOMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
DCD SWI2_EGU2_IRQHandler
DCD SWI3_EGU3_IRQHandler
DCD SWI4_EGU4_IRQHandler
DCD SWI5_EGU5_IRQHandler
DCD TIMER3_IRQHandler
DCD TIMER4_IRQHandler
DCD PWM0_IRQHandler
DCD PDM_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD MWU_IRQHandler
DCD PWM1_IRQHandler
DCD PWM2_IRQHandler
DCD SPIM2_SPIS2_SPI2_IRQHandler
DCD RTC2_IRQHandler
DCD I2S_IRQHandler
DCD FPU_IRQHandler
DCD USBD_IRQHandler
DCD UARTE1_IRQHandler
DCD QSPI_IRQHandler
DCD CRYPTOCELL_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PWM3_IRQHandler
DCD 0 ; Reserved
DCD SPIM3_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemoryManagement_Handler\
PROC
EXPORT MemoryManagement_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
EXPORT NFCT_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT SAADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
EXPORT SWI2_EGU2_IRQHandler [WEAK]
EXPORT SWI3_EGU3_IRQHandler [WEAK]
EXPORT SWI4_EGU4_IRQHandler [WEAK]
EXPORT SWI5_EGU5_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PDM_IRQHandler [WEAK]
EXPORT MWU_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT UARTE1_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT CRYPTOCELL_IRQHandler [WEAK]
EXPORT PWM3_IRQHandler [WEAK]
EXPORT SPIM3_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
NFCT_IRQHandler
GPIOTE_IRQHandler
SAADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
COMP_LPCOMP_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
SWI2_EGU2_IRQHandler
SWI3_EGU3_IRQHandler
SWI4_EGU4_IRQHandler
SWI5_EGU5_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
PWM0_IRQHandler
PDM_IRQHandler
MWU_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
SPIM2_SPIS2_SPI2_IRQHandler
RTC2_IRQHandler
I2S_IRQHandler
FPU_IRQHandler
USBD_IRQHandler
UARTE1_IRQHandler
QSPI_IRQHandler
CRYPTOCELL_IRQHandler
PWM3_IRQHandler
SPIM3_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

329
project/dfu/secure_bootloader/pca10056_s140_ble/arm5_no_packs/RTE/Device/nRF52840_xxAA/system_nrf52.c Normal file
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "nrf_peripherals.h"
#include "nrf52_erratas.h"
#include "system_nrf52.h"
#include "system_nrf52_approtect.h"
#define __SYSTEM_CLOCK_64M (64000000UL)
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#endif
/* Select correct reset pin */
/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */
#if defined (DEVELOP_IN_NRF52805) \
|| defined (DEVELOP_IN_NRF52810) \
|| defined (DEVELOP_IN_NRF52811) \
|| defined (DEVELOP_IN_NRF52832)
#define RESET_PIN 21
#elif defined (DEVELOP_IN_NRF52820) \
|| defined (DEVELOP_IN_NRF52833) \
|| defined (DEVELOP_IN_NRF52840)
#define RESET_PIN 18
#elif defined (NRF52805_XXAA) \
|| defined (NRF52810_XXAA) \
|| defined (NRF52811_XXAA) \
|| defined (NRF52832_XXAA) \
|| defined (NRF52832_XXAB)
#define RESET_PIN 21
#elif defined (NRF52820_XXAA) \
|| defined (NRF52833_XXAA) \
|| defined (NRF52840_XXAA)
#define RESET_PIN 18
#else
#error "A supported device macro must be defined."
#endif
/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
}
/* Configure the NVMC to "mode".
Mode must be an enumerator of field NVMC_CONFIG_WEN */
void nvmc_config(uint32_t mode)
{
NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
nvmc_wait();
}
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK_64M;
}
void SystemInit(void)
{
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#if NRF52_ERRATA_12_ENABLE_WORKAROUND
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_12()){
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
}
#endif
#if NRF52_ERRATA_16_ENABLE_WORKAROUND
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_16()){
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
}
#endif
#if NRF52_ERRATA_31_ENABLE_WORKAROUND
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
#endif
#if NRF52_ERRATA_32_ENABLE_WORKAROUND
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
#endif
#if NRF52_ERRATA_36_ENABLE_WORKAROUND
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
}
#endif
#if NRF52_ERRATA_37_ENABLE_WORKAROUND
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
#endif
#if NRF52_ERRATA_57_ENABLE_WORKAROUND
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_57()){
*(volatile uint32_t *)0x40005610 = 0x00000005;
*(volatile uint32_t *)0x40005688 = 0x00000001;
*(volatile uint32_t *)0x40005618 = 0x00000000;
*(volatile uint32_t *)0x40005614 = 0x0000003F;
}
#endif
#if NRF52_ERRATA_66_ENABLE_WORKAROUND
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
}
#endif
#if NRF52_ERRATA_98_ENABLE_WORKAROUND
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_98()){
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
}
#endif
#if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
#endif
#if NRF52_ERRATA_108_ENABLE_WORKAROUND
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_108()){
*(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
}
#endif
#if NRF52_ERRATA_115_ENABLE_WORKAROUND
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_115()){
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
}
#endif
#if NRF52_ERRATA_120_ENABLE_WORKAROUND
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_120()){
*(volatile uint32_t *)0x40029640ul = 0x200ul;
}
#endif
#if NRF52_ERRATA_136_ENABLE_WORKAROUND
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
#endif
#if NRF52_ERRATA_182_ENABLE_WORKAROUND
/* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_182()){
*(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
}
#endif
#if NRF52_ERRATA_217_ENABLE_WORKAROUND
/* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_217()){
*(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful;
}
#endif
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
nrf52_handle_approtect();
#if NRF52_CONFIGURATION_249_ENABLE && (defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || defined(NRF52811_XXAA))
if (nrf52_configuration_249() && (NRF_UICR->NRFMDK[0] == 0xFFFFFFFF || NRF_UICR->NRFMDK[1] == 0xFFFFFFFF))
{
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NRFMDK[0] = 0;
nvmc_wait();
NRF_UICR->NRFMDK[1] = 0;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
}
#endif
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS) && defined(NFCT_PRESENT)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->PSELRESET[0] = RESET_PIN;
nvmc_wait();
NRF_UICR->PSELRESET[1] = RESET_PIN;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* When developing for nRF52810 on an nRF52832, or nRF52811 on an nRF52840,
make sure NFC pins are mapped as GPIO. */
#if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \
|| defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA)
if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){
nvmc_config(NVMC_CONFIG_WEN_Wen);
*((uint32_t *)0x1000120C) = 0;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
SystemCoreClockUpdate();
}

21
project/dfu/secure_bootloader/pca10056_s140_ble/arm5_no_packs/RTE/_nrf52840_xxaa_s140/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'secure_bootloader_ble_s140_pca10056'
* Target: 'nrf52840_xxaa_s140'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "nrf.h"
#endif /* RTE_COMPONENTS_H */

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