Initial commit: MT firmware project
- BLE peripheral applications - dr_piezo and bladder_patch projects Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
This commit is contained in:
Charles Kwon
@@ -0,0 +1,261 @@
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; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
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;
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; SPDX-License-Identifier: Apache-2.0
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;
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; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
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||||
; www.apache.org/licenses/LICENSE-2.0
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||||
;
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||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
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||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
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IF :DEF: __STARTUP_CONFIG
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#ifdef __STARTUP_CONFIG
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#include "startup_config.h"
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#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
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#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
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#endif
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#endif
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ENDIF
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IF :DEF: __STARTUP_CONFIG
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Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
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ELIF :DEF: __STACK_SIZE
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Stack_Size EQU __STACK_SIZE
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ELSE
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Stack_Size EQU 2048
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ENDIF
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IF :DEF: __STARTUP_CONFIG
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Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
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ELSE
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Stack_Align EQU 3
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ENDIF
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AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
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Stack_Mem SPACE Stack_Size
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__initial_sp
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IF :DEF: __STARTUP_CONFIG
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Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
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ELIF :DEF: __HEAP_SIZE
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Heap_Size EQU __HEAP_SIZE
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ELSE
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Heap_Size EQU 2048
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ENDIF
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler
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DCD SysTick_Handler
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; External Interrupts
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DCD POWER_CLOCK_IRQHandler
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DCD RADIO_IRQHandler
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DCD UART0_IRQHandler
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DCD SPI0_TWI0_IRQHandler
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DCD SPI1_TWI1_IRQHandler
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DCD 0 ; Reserved
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DCD GPIOTE_IRQHandler
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DCD ADC_IRQHandler
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DCD TIMER0_IRQHandler
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DCD TIMER1_IRQHandler
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DCD TIMER2_IRQHandler
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DCD RTC0_IRQHandler
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DCD TEMP_IRQHandler
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DCD RNG_IRQHandler
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DCD ECB_IRQHandler
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DCD CCM_AAR_IRQHandler
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DCD WDT_IRQHandler
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DCD RTC1_IRQHandler
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DCD QDEC_IRQHandler
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DCD LPCOMP_IRQHandler
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DCD SWI0_IRQHandler
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DCD SWI1_IRQHandler
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DCD SWI2_IRQHandler
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DCD SWI3_IRQHandler
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DCD SWI4_IRQHandler
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DCD SWI5_IRQHandler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
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NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address
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NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
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LDR R0, =NRF_POWER_RAMON_ADDRESS
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LDR R2, [R0]
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ORRS R2, R2, R1
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STR R2, [R0]
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LDR R0, =NRF_POWER_RAMONB_ADDRESS
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LDR R2, [R0]
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ORRS R2, R2, R1
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STR R2, [R0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT POWER_CLOCK_IRQHandler [WEAK]
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EXPORT RADIO_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT SPI0_TWI0_IRQHandler [WEAK]
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EXPORT SPI1_TWI1_IRQHandler [WEAK]
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EXPORT GPIOTE_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT RTC0_IRQHandler [WEAK]
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EXPORT TEMP_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT ECB_IRQHandler [WEAK]
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EXPORT CCM_AAR_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT RTC1_IRQHandler [WEAK]
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EXPORT QDEC_IRQHandler [WEAK]
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EXPORT LPCOMP_IRQHandler [WEAK]
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EXPORT SWI0_IRQHandler [WEAK]
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EXPORT SWI1_IRQHandler [WEAK]
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EXPORT SWI2_IRQHandler [WEAK]
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EXPORT SWI3_IRQHandler [WEAK]
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EXPORT SWI4_IRQHandler [WEAK]
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EXPORT SWI5_IRQHandler [WEAK]
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POWER_CLOCK_IRQHandler
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RADIO_IRQHandler
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UART0_IRQHandler
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SPI0_TWI0_IRQHandler
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SPI1_TWI1_IRQHandler
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GPIOTE_IRQHandler
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ADC_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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RTC0_IRQHandler
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TEMP_IRQHandler
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RNG_IRQHandler
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ECB_IRQHandler
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CCM_AAR_IRQHandler
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WDT_IRQHandler
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RTC1_IRQHandler
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QDEC_IRQHandler
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LPCOMP_IRQHandler
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SWI0_IRQHandler
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SWI1_IRQHandler
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SWI2_IRQHandler
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SWI3_IRQHandler
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SWI4_IRQHandler
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SWI5_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, = (Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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@@ -0,0 +1,371 @@
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; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
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||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
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||||
#include "startup_config.h"
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#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
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#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
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#endif
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#endif
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ENDIF
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IF :DEF: __STARTUP_CONFIG
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Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
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ELIF :DEF: __STACK_SIZE
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Stack_Size EQU __STACK_SIZE
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ELSE
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Stack_Size EQU 4096
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ENDIF
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IF :DEF: __STARTUP_CONFIG
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Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
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ELSE
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Stack_Align EQU 3
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ENDIF
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AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
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Stack_Mem SPACE Stack_Size
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__initial_sp
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IF :DEF: __STARTUP_CONFIG
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Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
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ELIF :DEF: __HEAP_SIZE
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Heap_Size EQU __HEAP_SIZE
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||||
ELSE
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Heap_Size EQU 4096
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ENDIF
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||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
|
||||
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
|
||||
EXPORT NFCT_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_EGU2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_EGU3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_EGU4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_EGU5_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PDM_IRQHandler [WEAK]
|
||||
EXPORT MWU_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT PWM2_IRQHandler [WEAK]
|
||||
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
|
||||
EXPORT RTC2_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
NFCT_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
COMP_LPCOMP_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_EGU2_IRQHandler
|
||||
SWI3_EGU3_IRQHandler
|
||||
SWI4_EGU4_IRQHandler
|
||||
SWI5_EGU5_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PDM_IRQHandler
|
||||
MWU_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
PWM2_IRQHandler
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
RTC2_IRQHandler
|
||||
I2S_IRQHandler
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,345 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD TWIM0_TWIS0_TWI0_IRQHandler
|
||||
DCD SPIM0_SPIS0_SPI0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD SWI4_IRQHandler
|
||||
DCD SWI5_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT TWIM0_TWIS0_TWI0_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_SPI0_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
TWIM0_TWIS0_TWI0_IRQHandler
|
||||
SPIM0_SPIS0_SPI0_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_IRQHandler
|
||||
SWI3_IRQHandler
|
||||
SWI4_IRQHandler
|
||||
SWI5_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,374 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD TWIM0_TWIS0_TWI0_IRQHandler
|
||||
DCD SPIM0_SPIS0_SPI0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD SWI4_IRQHandler
|
||||
DCD SWI5_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
; Workaround for Errata 185 RAM: RAM corruption at extreme corners
|
||||
; found at the Errata document for your device located
|
||||
; at https://infocenter.nordicsemi.com/index.jsp
|
||||
|
||||
LDR R0, =0x10000130
|
||||
LDR R0, [R0]
|
||||
LDR R1, =0x10000134
|
||||
LDR R1, [R1]
|
||||
|
||||
CMP R0, #0xA
|
||||
BNE skip
|
||||
CMP R1, #0x0
|
||||
BNE skip
|
||||
|
||||
LDR R0, =0x40000EE4
|
||||
LDR R2, [R0]
|
||||
LDR R3, =0xFFFFFF8F
|
||||
ANDS R2, R2, R3
|
||||
LDR R3, =0x00000040
|
||||
ORRS R2, R2, R3
|
||||
STR R2, [R0]
|
||||
|
||||
skip
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT TWIM0_TWIS0_TWI0_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_SPI0_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PDM_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
TWIM0_TWIS0_TWI0_IRQHandler
|
||||
SPIM0_SPIS0_SPI0_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
COMP_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_IRQHandler
|
||||
SWI3_IRQHandler
|
||||
SWI4_IRQHandler
|
||||
SWI5_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,351 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
DCD SPIM0_SPIS0_SPI0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD SWI4_IRQHandler
|
||||
DCD SWI5_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_SPI0_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PDM_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
SPIM0_SPIS0_SPI0_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
COMP_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_IRQHandler
|
||||
SWI3_IRQHandler
|
||||
SWI4_IRQHandler
|
||||
SWI5_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,349 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 2048
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USBD_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
|
||||
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_EGU2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_EGU3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_EGU4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_EGU5_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
COMP_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_EGU2_IRQHandler
|
||||
SWI3_EGU3_IRQHandler
|
||||
SWI4_EGU4_IRQHandler
|
||||
SWI5_EGU5_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
USBD_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,379 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 8192
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 8192
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD UARTE1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SPIM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
|
||||
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
|
||||
EXPORT NFCT_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_EGU2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_EGU3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_EGU4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_EGU5_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PDM_IRQHandler [WEAK]
|
||||
EXPORT MWU_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT PWM2_IRQHandler [WEAK]
|
||||
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
|
||||
EXPORT RTC2_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT UARTE1_IRQHandler [WEAK]
|
||||
EXPORT PWM3_IRQHandler [WEAK]
|
||||
EXPORT SPIM3_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
NFCT_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
COMP_LPCOMP_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_EGU2_IRQHandler
|
||||
SWI3_EGU3_IRQHandler
|
||||
SWI4_EGU4_IRQHandler
|
||||
SWI5_EGU5_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PDM_IRQHandler
|
||||
MWU_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
PWM2_IRQHandler
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
RTC2_IRQHandler
|
||||
I2S_IRQHandler
|
||||
FPU_IRQHandler
|
||||
USBD_IRQHandler
|
||||
UARTE1_IRQHandler
|
||||
PWM3_IRQHandler
|
||||
SPIM3_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,383 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 16384
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 16384
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD UARTE1_IRQHandler
|
||||
DCD QSPI_IRQHandler
|
||||
DCD CRYPTOCELL_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SPIM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT POWER_CLOCK_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_UART0_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
|
||||
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
|
||||
EXPORT NFCT_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT CCM_AAR_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT QDEC_IRQHandler [WEAK]
|
||||
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
|
||||
EXPORT SWI0_EGU0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_EGU1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_EGU2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_EGU3_IRQHandler [WEAK]
|
||||
EXPORT SWI4_EGU4_IRQHandler [WEAK]
|
||||
EXPORT SWI5_EGU5_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PDM_IRQHandler [WEAK]
|
||||
EXPORT MWU_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT PWM2_IRQHandler [WEAK]
|
||||
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
|
||||
EXPORT RTC2_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT UARTE1_IRQHandler [WEAK]
|
||||
EXPORT QSPI_IRQHandler [WEAK]
|
||||
EXPORT CRYPTOCELL_IRQHandler [WEAK]
|
||||
EXPORT PWM3_IRQHandler [WEAK]
|
||||
EXPORT SPIM3_IRQHandler [WEAK]
|
||||
POWER_CLOCK_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
UARTE0_UART0_IRQHandler
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
NFCT_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RNG_IRQHandler
|
||||
ECB_IRQHandler
|
||||
CCM_AAR_IRQHandler
|
||||
WDT_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
QDEC_IRQHandler
|
||||
COMP_LPCOMP_IRQHandler
|
||||
SWI0_EGU0_IRQHandler
|
||||
SWI1_EGU1_IRQHandler
|
||||
SWI2_EGU2_IRQHandler
|
||||
SWI3_EGU3_IRQHandler
|
||||
SWI4_EGU4_IRQHandler
|
||||
SWI5_EGU5_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PDM_IRQHandler
|
||||
MWU_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
PWM2_IRQHandler
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
RTC2_IRQHandler
|
||||
I2S_IRQHandler
|
||||
FPU_IRQHandler
|
||||
USBD_IRQHandler
|
||||
UARTE1_IRQHandler
|
||||
QSPI_IRQHandler
|
||||
CRYPTOCELL_IRQHandler
|
||||
PWM3_IRQHandler
|
||||
SPIM3_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,512 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 16384
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 16384
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD SecureFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD FPU_IRQHandler
|
||||
DCD CACHE_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD CLOCK_POWER_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
|
||||
DCD SPIM4_IRQHandler
|
||||
DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
|
||||
DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
|
||||
DCD GPIOTE0_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC0_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD WDT0_IRQHandler
|
||||
DCD WDT1_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD EGU0_IRQHandler
|
||||
DCD EGU1_IRQHandler
|
||||
DCD EGU2_IRQHandler
|
||||
DCD EGU3_IRQHandler
|
||||
DCD EGU4_IRQHandler
|
||||
DCD EGU5_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD PDM0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD I2S0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD IPC_IRQHandler
|
||||
DCD QSPI_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD NFCT_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD QDEC0_IRQHandler
|
||||
DCD QDEC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD USBD_IRQHandler
|
||||
DCD USBREGULATOR_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD KMU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CRYPTOCELL_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SecureFault_Handler\
|
||||
PROC
|
||||
EXPORT SecureFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT CACHE_IRQHandler [WEAK]
|
||||
EXPORT SPU_IRQHandler [WEAK]
|
||||
EXPORT CLOCK_POWER_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler [WEAK]
|
||||
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler [WEAK]
|
||||
EXPORT SPIM4_IRQHandler [WEAK]
|
||||
EXPORT SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler [WEAK]
|
||||
EXPORT SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE0_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT WDT0_IRQHandler [WEAK]
|
||||
EXPORT WDT1_IRQHandler [WEAK]
|
||||
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
|
||||
EXPORT EGU0_IRQHandler [WEAK]
|
||||
EXPORT EGU1_IRQHandler [WEAK]
|
||||
EXPORT EGU2_IRQHandler [WEAK]
|
||||
EXPORT EGU3_IRQHandler [WEAK]
|
||||
EXPORT EGU4_IRQHandler [WEAK]
|
||||
EXPORT EGU5_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT PWM2_IRQHandler [WEAK]
|
||||
EXPORT PWM3_IRQHandler [WEAK]
|
||||
EXPORT PDM0_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT IPC_IRQHandler [WEAK]
|
||||
EXPORT QSPI_IRQHandler [WEAK]
|
||||
EXPORT NFCT_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE1_IRQHandler [WEAK]
|
||||
EXPORT QDEC0_IRQHandler [WEAK]
|
||||
EXPORT QDEC1_IRQHandler [WEAK]
|
||||
EXPORT USBD_IRQHandler [WEAK]
|
||||
EXPORT USBREGULATOR_IRQHandler [WEAK]
|
||||
EXPORT KMU_IRQHandler [WEAK]
|
||||
EXPORT CRYPTOCELL_IRQHandler [WEAK]
|
||||
FPU_IRQHandler
|
||||
CACHE_IRQHandler
|
||||
SPU_IRQHandler
|
||||
CLOCK_POWER_IRQHandler
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
|
||||
SPIM4_IRQHandler
|
||||
SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
|
||||
SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
|
||||
GPIOTE0_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
WDT0_IRQHandler
|
||||
WDT1_IRQHandler
|
||||
COMP_LPCOMP_IRQHandler
|
||||
EGU0_IRQHandler
|
||||
EGU1_IRQHandler
|
||||
EGU2_IRQHandler
|
||||
EGU3_IRQHandler
|
||||
EGU4_IRQHandler
|
||||
EGU5_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
PWM2_IRQHandler
|
||||
PWM3_IRQHandler
|
||||
PDM0_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
IPC_IRQHandler
|
||||
QSPI_IRQHandler
|
||||
NFCT_IRQHandler
|
||||
GPIOTE1_IRQHandler
|
||||
QDEC0_IRQHandler
|
||||
QDEC1_IRQHandler
|
||||
USBD_IRQHandler
|
||||
USBREGULATOR_IRQHandler
|
||||
KMU_IRQHandler
|
||||
CRYPTOCELL_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,354 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 4096
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 4096
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CLOCK_POWER_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD RADIO_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD AAR_CCM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD IPC_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
DCD EGU0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD SWI0_IRQHandler
|
||||
DCD SWI1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT CLOCK_POWER_IRQHandler [WEAK]
|
||||
EXPORT RADIO_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT ECB_IRQHandler [WEAK]
|
||||
EXPORT AAR_CCM_IRQHandler [WEAK]
|
||||
EXPORT TEMP_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT IPC_IRQHandler [WEAK]
|
||||
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler [WEAK]
|
||||
EXPORT EGU0_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT SWI0_IRQHandler [WEAK]
|
||||
EXPORT SWI1_IRQHandler [WEAK]
|
||||
EXPORT SWI2_IRQHandler [WEAK]
|
||||
EXPORT SWI3_IRQHandler [WEAK]
|
||||
CLOCK_POWER_IRQHandler
|
||||
RADIO_IRQHandler
|
||||
RNG_IRQHandler
|
||||
GPIOTE_IRQHandler
|
||||
WDT_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
ECB_IRQHandler
|
||||
AAR_CCM_IRQHandler
|
||||
TEMP_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
IPC_IRQHandler
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
EGU0_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
SWI0_IRQHandler
|
||||
SWI1_IRQHandler
|
||||
SWI2_IRQHandler
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,492 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
|
||||
ELIF :DEF: __STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 16384
|
||||
ENDIF
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
ELSE
|
||||
Stack_Align EQU 3
|
||||
ENDIF
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
IF :DEF: __STARTUP_CONFIG
|
||||
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
|
||||
ELIF :DEF: __HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 16384
|
||||
ENDIF
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD SecureFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD CLOCK_POWER_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
|
||||
DCD UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
|
||||
DCD UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
|
||||
DCD UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE0_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC0_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD WDT_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EGU0_IRQHandler
|
||||
DCD EGU1_IRQHandler
|
||||
DCD EGU2_IRQHandler
|
||||
DCD EGU3_IRQHandler
|
||||
DCD EGU4_IRQHandler
|
||||
DCD EGU5_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD I2S_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD IPC_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD KMU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CRYPTOCELL_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemoryManagement_Handler\
|
||||
PROC
|
||||
EXPORT MemoryManagement_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SecureFault_Handler\
|
||||
PROC
|
||||
EXPORT SecureFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT SPU_IRQHandler [WEAK]
|
||||
EXPORT CLOCK_POWER_IRQHandler [WEAK]
|
||||
EXPORT UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler [WEAK]
|
||||
EXPORT UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler [WEAK]
|
||||
EXPORT UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler [WEAK]
|
||||
EXPORT UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE0_IRQHandler [WEAK]
|
||||
EXPORT SAADC_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT RTC0_IRQHandler [WEAK]
|
||||
EXPORT RTC1_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT EGU0_IRQHandler [WEAK]
|
||||
EXPORT EGU1_IRQHandler [WEAK]
|
||||
EXPORT EGU2_IRQHandler [WEAK]
|
||||
EXPORT EGU3_IRQHandler [WEAK]
|
||||
EXPORT EGU4_IRQHandler [WEAK]
|
||||
EXPORT EGU5_IRQHandler [WEAK]
|
||||
EXPORT PWM0_IRQHandler [WEAK]
|
||||
EXPORT PWM1_IRQHandler [WEAK]
|
||||
EXPORT PWM2_IRQHandler [WEAK]
|
||||
EXPORT PWM3_IRQHandler [WEAK]
|
||||
EXPORT PDM_IRQHandler [WEAK]
|
||||
EXPORT I2S_IRQHandler [WEAK]
|
||||
EXPORT IPC_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT GPIOTE1_IRQHandler [WEAK]
|
||||
EXPORT KMU_IRQHandler [WEAK]
|
||||
EXPORT CRYPTOCELL_IRQHandler [WEAK]
|
||||
SPU_IRQHandler
|
||||
CLOCK_POWER_IRQHandler
|
||||
UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
|
||||
UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
|
||||
UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
|
||||
UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
|
||||
GPIOTE0_IRQHandler
|
||||
SAADC_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
RTC0_IRQHandler
|
||||
RTC1_IRQHandler
|
||||
WDT_IRQHandler
|
||||
EGU0_IRQHandler
|
||||
EGU1_IRQHandler
|
||||
EGU2_IRQHandler
|
||||
EGU3_IRQHandler
|
||||
EGU4_IRQHandler
|
||||
EGU5_IRQHandler
|
||||
PWM0_IRQHandler
|
||||
PWM1_IRQHandler
|
||||
PWM2_IRQHandler
|
||||
PWM3_IRQHandler
|
||||
PDM_IRQHandler
|
||||
I2S_IRQHandler
|
||||
IPC_IRQHandler
|
||||
FPU_IRQHandler
|
||||
GPIOTE1_IRQHandler
|
||||
KMU_IRQHandler
|
||||
CRYPTOCELL_IRQHandler
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,264 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _COMPILER_ABSTRACTION_H
|
||||
#define _COMPILER_ABSTRACTION_H
|
||||
|
||||
/*lint ++flb "Enter library region" */
|
||||
|
||||
#ifndef NRF_STRING_CONCATENATE_IMPL
|
||||
#define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs
|
||||
#endif
|
||||
#ifndef NRF_STRING_CONCATENATE
|
||||
#define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs)
|
||||
#endif
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __align(n)
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif
|
||||
|
||||
#define GET_SP() __current_sp()
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#define NRF_STATIC_ASSERT(cond, msg) \
|
||||
;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __attribute__((aligned(n)))
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif
|
||||
|
||||
#define GET_SP() __current_sp()
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#ifdef __cplusplus
|
||||
#ifndef _Static_assert
|
||||
#define _Static_assert static_assert
|
||||
#endif
|
||||
#endif
|
||||
#define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __attribute__((aligned(x)))
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
#else
|
||||
#ifndef __ALIGN
|
||||
#define STRING_PRAGMA(x) _Pragma(#x)
|
||||
#define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_SP()
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ ) || defined ( __clang__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __attribute__((aligned(n)))
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif
|
||||
|
||||
#define GET_SP() gcc_current_sp()
|
||||
|
||||
static inline unsigned int gcc_current_sp(void)
|
||||
{
|
||||
unsigned int stack_pointer = 0;
|
||||
__asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer));
|
||||
return stack_pointer;
|
||||
}
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#ifdef __cplusplus
|
||||
#ifndef _Static_assert
|
||||
#define _Static_assert static_assert
|
||||
#endif
|
||||
#endif
|
||||
#define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGN
|
||||
#define __ALIGN(n) __align(n)
|
||||
#endif
|
||||
|
||||
/* Not defined for TASKING. */
|
||||
#ifndef __PACKED
|
||||
#define __PACKED
|
||||
#endif
|
||||
|
||||
#ifndef __UNUSED
|
||||
#define __UNUSED __attribute__((unused))
|
||||
#endif
|
||||
|
||||
#define GET_SP() __get_MSP()
|
||||
|
||||
#ifndef NRF_STATIC_ASSERT
|
||||
#define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \
|
||||
NRF_STATIC_ASSERT( \
|
||||
( \
|
||||
(major < MDK_MAJOR_VERSION) || \
|
||||
(major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \
|
||||
(major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \
|
||||
), "MDK version mismatch.")
|
||||
|
||||
#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \
|
||||
NRF_STATIC_ASSERT( \
|
||||
( \
|
||||
(major != MDK_MAJOR_VERSION) || \
|
||||
(major != MDK_MAJOR_VERSION) || \
|
||||
(major != MDK_MAJOR_VERSION) \
|
||||
), "MDK version mismatch.")
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,300 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 2048
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 2048
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UART0_IRQHandler
|
||||
.long SPI0_TWI0_IRQHandler
|
||||
.long SPI1_TWI1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE_IRQHandler
|
||||
.long ADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long LPCOMP_IRQHandler
|
||||
.long SWI0_IRQHandler
|
||||
.long SWI1_IRQHandler
|
||||
.long SWI2_IRQHandler
|
||||
.long SWI3_IRQHandler
|
||||
.long SWI4_IRQHandler
|
||||
.long SWI5_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
|
||||
.equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
|
||||
.equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
|
||||
|
||||
LDR R0, =NRF_POWER_RAMON_ADDRESS
|
||||
LDR R2, [R0]
|
||||
ORRS R2, R1
|
||||
STR R2, [R0]
|
||||
|
||||
LDR R0, =NRF_POWER_RAMONB_ADDRESS
|
||||
LDR R2, [R0]
|
||||
ORRS R2, R1
|
||||
STR R2, [R0]
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UART0_IRQHandler
|
||||
IRQ SPI0_TWI0_IRQHandler
|
||||
IRQ SPI1_TWI1_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ ADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ LPCOMP_IRQHandler
|
||||
IRQ SWI0_IRQHandler
|
||||
IRQ SWI1_IRQHandler
|
||||
IRQ SWI2_IRQHandler
|
||||
IRQ SWI3_IRQHandler
|
||||
IRQ SWI4_IRQHandler
|
||||
IRQ SWI5_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,406 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 4096
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 4096
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
.long NFCT_IRQHandler
|
||||
.long GPIOTE_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long COMP_LPCOMP_IRQHandler
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_EGU2_IRQHandler
|
||||
.long SWI3_EGU3_IRQHandler
|
||||
.long SWI4_EGU4_IRQHandler
|
||||
.long SWI5_EGU5_IRQHandler
|
||||
.long TIMER3_IRQHandler
|
||||
.long TIMER4_IRQHandler
|
||||
.long PWM0_IRQHandler
|
||||
.long PDM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long MWU_IRQHandler
|
||||
.long PWM1_IRQHandler
|
||||
.long PWM2_IRQHandler
|
||||
.long SPIM2_SPIS2_SPI2_IRQHandler
|
||||
.long RTC2_IRQHandler
|
||||
.long I2S_IRQHandler
|
||||
.long FPU_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
IRQ NFCT_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_LPCOMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_EGU2_IRQHandler
|
||||
IRQ SWI3_EGU3_IRQHandler
|
||||
IRQ SWI4_EGU4_IRQHandler
|
||||
IRQ SWI5_EGU5_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ TIMER4_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
IRQ MWU_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ PWM2_IRQHandler
|
||||
IRQ SPIM2_SPIS2_SPI2_IRQHandler
|
||||
IRQ RTC2_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
IRQ FPU_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,393 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 2048
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 2048
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long TWIM0_TWIS0_TWI0_IRQHandler
|
||||
.long SPIM0_SPIS0_SPI0_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_IRQHandler
|
||||
.long SWI3_IRQHandler
|
||||
.long SWI4_IRQHandler
|
||||
.long SWI5_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ TWIM0_TWIS0_TWI0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_SPI0_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_IRQHandler
|
||||
IRQ SWI3_IRQHandler
|
||||
IRQ SWI4_IRQHandler
|
||||
IRQ SWI5_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,419 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 2048
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 2048
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long TWIM0_TWIS0_TWI0_IRQHandler
|
||||
.long SPIM0_SPIS0_SPI0_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long COMP_IRQHandler
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_IRQHandler
|
||||
.long SWI3_IRQHandler
|
||||
.long SWI4_IRQHandler
|
||||
.long SWI5_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long PWM0_IRQHandler
|
||||
.long PDM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Workaround for Errata 185 RAM: RAM corruption at extreme corners
|
||||
* found at the Errata document for your device located
|
||||
* at https://infocenter.nordicsemi.com/index.jsp */
|
||||
|
||||
LDR R0, =0x10000130
|
||||
LDR R0, [R0]
|
||||
LDR R1, =0x10000134
|
||||
LDR R1, [R1]
|
||||
|
||||
CMP R0, #0xA
|
||||
BNE skip
|
||||
CMP R1, #0x0
|
||||
BNE skip
|
||||
|
||||
LDR R0, =0x40000EE4
|
||||
LDR R2, [R0]
|
||||
LDR R3, =0xFFFFFF8F
|
||||
ANDS R2, R2, R3
|
||||
LDR R3, =0x00000040
|
||||
ORRS R2, R2, R3
|
||||
STR R2, [R0]
|
||||
|
||||
skip:
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ TWIM0_TWIS0_TWI0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_SPI0_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_IRQHandler
|
||||
IRQ SWI3_IRQHandler
|
||||
IRQ SWI4_IRQHandler
|
||||
IRQ SWI5_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,396 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 2048
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 2048
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
.long SPIM0_SPIS0_SPI0_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long COMP_IRQHandler
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_IRQHandler
|
||||
.long SWI3_IRQHandler
|
||||
.long SWI4_IRQHandler
|
||||
.long SWI5_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long PWM0_IRQHandler
|
||||
.long PDM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
IRQ SPIM0_SPIS0_SPI0_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_IRQHandler
|
||||
IRQ SWI3_IRQHandler
|
||||
IRQ SWI4_IRQHandler
|
||||
IRQ SWI5_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,395 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 2048
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 2048
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long COMP_IRQHandler
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_EGU2_IRQHandler
|
||||
.long SWI3_EGU3_IRQHandler
|
||||
.long SWI4_EGU4_IRQHandler
|
||||
.long SWI5_EGU5_IRQHandler
|
||||
.long TIMER3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long USBD_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_EGU2_IRQHandler
|
||||
IRQ SWI3_EGU3_IRQHandler
|
||||
IRQ SWI4_EGU4_IRQHandler
|
||||
IRQ SWI5_EGU5_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ USBD_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,410 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 8192
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 8192
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
.long NFCT_IRQHandler
|
||||
.long GPIOTE_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long COMP_LPCOMP_IRQHandler
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_EGU2_IRQHandler
|
||||
.long SWI3_EGU3_IRQHandler
|
||||
.long SWI4_EGU4_IRQHandler
|
||||
.long SWI5_EGU5_IRQHandler
|
||||
.long TIMER3_IRQHandler
|
||||
.long TIMER4_IRQHandler
|
||||
.long PWM0_IRQHandler
|
||||
.long PDM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long MWU_IRQHandler
|
||||
.long PWM1_IRQHandler
|
||||
.long PWM2_IRQHandler
|
||||
.long SPIM2_SPIS2_SPI2_IRQHandler
|
||||
.long RTC2_IRQHandler
|
||||
.long I2S_IRQHandler
|
||||
.long FPU_IRQHandler
|
||||
.long USBD_IRQHandler
|
||||
.long UARTE1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long PWM3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long SPIM3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
IRQ NFCT_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_LPCOMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_EGU2_IRQHandler
|
||||
IRQ SWI3_EGU3_IRQHandler
|
||||
IRQ SWI4_EGU4_IRQHandler
|
||||
IRQ SWI5_EGU5_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ TIMER4_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
IRQ MWU_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ PWM2_IRQHandler
|
||||
IRQ SPIM2_SPIS2_SPI2_IRQHandler
|
||||
IRQ RTC2_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
IRQ FPU_IRQHandler
|
||||
IRQ USBD_IRQHandler
|
||||
IRQ UARTE1_IRQHandler
|
||||
IRQ PWM3_IRQHandler
|
||||
IRQ SPIM3_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,412 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 16384
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 16384
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long POWER_CLOCK_IRQHandler
|
||||
.long RADIO_IRQHandler
|
||||
.long UARTE0_UART0_IRQHandler
|
||||
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
.long NFCT_IRQHandler
|
||||
.long GPIOTE_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long TEMP_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long CCM_AAR_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long QDEC_IRQHandler
|
||||
.long COMP_LPCOMP_IRQHandler
|
||||
.long SWI0_EGU0_IRQHandler
|
||||
.long SWI1_EGU1_IRQHandler
|
||||
.long SWI2_EGU2_IRQHandler
|
||||
.long SWI3_EGU3_IRQHandler
|
||||
.long SWI4_EGU4_IRQHandler
|
||||
.long SWI5_EGU5_IRQHandler
|
||||
.long TIMER3_IRQHandler
|
||||
.long TIMER4_IRQHandler
|
||||
.long PWM0_IRQHandler
|
||||
.long PDM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long MWU_IRQHandler
|
||||
.long PWM1_IRQHandler
|
||||
.long PWM2_IRQHandler
|
||||
.long SPIM2_SPIS2_SPI2_IRQHandler
|
||||
.long RTC2_IRQHandler
|
||||
.long I2S_IRQHandler
|
||||
.long FPU_IRQHandler
|
||||
.long USBD_IRQHandler
|
||||
.long UARTE1_IRQHandler
|
||||
.long QSPI_IRQHandler
|
||||
.long CRYPTOCELL_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long PWM3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long SPIM3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ POWER_CLOCK_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ UARTE0_UART0_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
IRQ NFCT_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ CCM_AAR_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ QDEC_IRQHandler
|
||||
IRQ COMP_LPCOMP_IRQHandler
|
||||
IRQ SWI0_EGU0_IRQHandler
|
||||
IRQ SWI1_EGU1_IRQHandler
|
||||
IRQ SWI2_EGU2_IRQHandler
|
||||
IRQ SWI3_EGU3_IRQHandler
|
||||
IRQ SWI4_EGU4_IRQHandler
|
||||
IRQ SWI5_EGU5_IRQHandler
|
||||
IRQ TIMER3_IRQHandler
|
||||
IRQ TIMER4_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
IRQ MWU_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ PWM2_IRQHandler
|
||||
IRQ SPIM2_SPIS2_SPI2_IRQHandler
|
||||
IRQ RTC2_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
IRQ FPU_IRQHandler
|
||||
IRQ USBD_IRQHandler
|
||||
IRQ UARTE1_IRQHandler
|
||||
IRQ QSPI_IRQHandler
|
||||
IRQ CRYPTOCELL_IRQHandler
|
||||
IRQ PWM3_IRQHandler
|
||||
IRQ SPIM3_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,545 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv8-m.main
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 16384
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 16384
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long SecureFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long FPU_IRQHandler
|
||||
.long CACHE_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long SPU_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long CLOCK_POWER_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
.long SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
|
||||
.long SPIM4_IRQHandler
|
||||
.long SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
|
||||
.long SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
|
||||
.long GPIOTE0_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long RTC0_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long WDT0_IRQHandler
|
||||
.long WDT1_IRQHandler
|
||||
.long COMP_LPCOMP_IRQHandler
|
||||
.long EGU0_IRQHandler
|
||||
.long EGU1_IRQHandler
|
||||
.long EGU2_IRQHandler
|
||||
.long EGU3_IRQHandler
|
||||
.long EGU4_IRQHandler
|
||||
.long EGU5_IRQHandler
|
||||
.long PWM0_IRQHandler
|
||||
.long PWM1_IRQHandler
|
||||
.long PWM2_IRQHandler
|
||||
.long PWM3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long PDM0_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long I2S0_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long IPC_IRQHandler
|
||||
.long QSPI_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long NFCT_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long QDEC0_IRQHandler
|
||||
.long QDEC1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long USBD_IRQHandler
|
||||
.long USBREGULATOR_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long KMU_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long CRYPTOCELL_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SecureFault_Handler
|
||||
.type SecureFault_Handler, %function
|
||||
SecureFault_Handler:
|
||||
b .
|
||||
.size SecureFault_Handler, . - SecureFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ FPU_IRQHandler
|
||||
IRQ CACHE_IRQHandler
|
||||
IRQ SPU_IRQHandler
|
||||
IRQ CLOCK_POWER_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
IRQ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
|
||||
IRQ SPIM4_IRQHandler
|
||||
IRQ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
|
||||
IRQ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
|
||||
IRQ GPIOTE0_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ WDT0_IRQHandler
|
||||
IRQ WDT1_IRQHandler
|
||||
IRQ COMP_LPCOMP_IRQHandler
|
||||
IRQ EGU0_IRQHandler
|
||||
IRQ EGU1_IRQHandler
|
||||
IRQ EGU2_IRQHandler
|
||||
IRQ EGU3_IRQHandler
|
||||
IRQ EGU4_IRQHandler
|
||||
IRQ EGU5_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ PWM2_IRQHandler
|
||||
IRQ PWM3_IRQHandler
|
||||
IRQ PDM0_IRQHandler
|
||||
IRQ I2S0_IRQHandler
|
||||
IRQ IPC_IRQHandler
|
||||
IRQ QSPI_IRQHandler
|
||||
IRQ NFCT_IRQHandler
|
||||
IRQ GPIOTE1_IRQHandler
|
||||
IRQ QDEC0_IRQHandler
|
||||
IRQ QDEC1_IRQHandler
|
||||
IRQ USBD_IRQHandler
|
||||
IRQ USBREGULATOR_IRQHandler
|
||||
IRQ KMU_IRQHandler
|
||||
IRQ CRYPTOCELL_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,406 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv8-m.main
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 4096
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 4096
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long CLOCK_POWER_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long RADIO_IRQHandler
|
||||
.long RNG_IRQHandler
|
||||
.long GPIOTE_IRQHandler
|
||||
.long WDT_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long ECB_IRQHandler
|
||||
.long AAR_CCM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long TEMP_IRQHandler
|
||||
.long RTC0_IRQHandler
|
||||
.long IPC_IRQHandler
|
||||
.long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
.long EGU0_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long RTC1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long SWI0_IRQHandler
|
||||
.long SWI1_IRQHandler
|
||||
.long SWI2_IRQHandler
|
||||
.long SWI3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ CLOCK_POWER_IRQHandler
|
||||
IRQ RADIO_IRQHandler
|
||||
IRQ RNG_IRQHandler
|
||||
IRQ GPIOTE_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ ECB_IRQHandler
|
||||
IRQ AAR_CCM_IRQHandler
|
||||
IRQ TEMP_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ IPC_IRQHandler
|
||||
IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
IRQ EGU0_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ SWI0_IRQHandler
|
||||
IRQ SWI1_IRQHandler
|
||||
IRQ SWI2_IRQHandler
|
||||
IRQ SWI3_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,535 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.arch armv8-m.main
|
||||
|
||||
#ifdef __STARTUP_CONFIG
|
||||
#include "startup_config.h"
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
.section .stack
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.align __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
.equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE
|
||||
#elif defined(__STACK_SIZE)
|
||||
.align 3
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.align 3
|
||||
.equ Stack_Size, 16384
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
.equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE
|
||||
#elif defined(__HEAP_SIZE)
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 16384
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector, "ax"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler
|
||||
.long NMI_Handler
|
||||
.long HardFault_Handler
|
||||
.long MemoryManagement_Handler
|
||||
.long BusFault_Handler
|
||||
.long UsageFault_Handler
|
||||
.long SecureFault_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SVC_Handler
|
||||
.long DebugMon_Handler
|
||||
.long 0 /*Reserved */
|
||||
.long PendSV_Handler
|
||||
.long SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long SPU_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long CLOCK_POWER_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
|
||||
.long UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
|
||||
.long UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
|
||||
.long UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE0_IRQHandler
|
||||
.long SAADC_IRQHandler
|
||||
.long TIMER0_IRQHandler
|
||||
.long TIMER1_IRQHandler
|
||||
.long TIMER2_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long RTC0_IRQHandler
|
||||
.long RTC1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long WDT_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long EGU0_IRQHandler
|
||||
.long EGU1_IRQHandler
|
||||
.long EGU2_IRQHandler
|
||||
.long EGU3_IRQHandler
|
||||
.long EGU4_IRQHandler
|
||||
.long EGU5_IRQHandler
|
||||
.long PWM0_IRQHandler
|
||||
.long PWM1_IRQHandler
|
||||
.long PWM2_IRQHandler
|
||||
.long PWM3_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long PDM_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long I2S_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long IPC_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long FPU_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long GPIOTE1_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long KMU_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long CRYPTOCELL_IRQHandler
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
.long 0 /*Reserved */
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
|
||||
/* Loop to copy data from read only memory to RAM.
|
||||
* The ranges of copy from/to are specified by following symbols:
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to.
|
||||
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
|
||||
* the user can add their own initialized data section before BSS section with the INSERT AFTER command.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifndef __STARTUP_SKIP_ETEXT
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__bss_start__
|
||||
|
||||
subs r3, r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
|
||||
* clears the RAM where BSS data is located.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Execute SystemInit function. */
|
||||
bl SystemInit
|
||||
|
||||
/* Call _start function provided by libraries.
|
||||
* If those libraries are not accessible, define __START as your entry point.
|
||||
*/
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler,.-Reset_Handler
|
||||
|
||||
.section ".text"
|
||||
|
||||
|
||||
/* Dummy Exception Handlers (infinite loops which can be modified) */
|
||||
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
b .
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
b .
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
|
||||
.weak MemoryManagement_Handler
|
||||
.type MemoryManagement_Handler, %function
|
||||
MemoryManagement_Handler:
|
||||
b .
|
||||
.size MemoryManagement_Handler, . - MemoryManagement_Handler
|
||||
|
||||
|
||||
.weak BusFault_Handler
|
||||
.type BusFault_Handler, %function
|
||||
BusFault_Handler:
|
||||
b .
|
||||
.size BusFault_Handler, . - BusFault_Handler
|
||||
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.type UsageFault_Handler, %function
|
||||
UsageFault_Handler:
|
||||
b .
|
||||
.size UsageFault_Handler, . - UsageFault_Handler
|
||||
|
||||
|
||||
.weak SecureFault_Handler
|
||||
.type SecureFault_Handler, %function
|
||||
SecureFault_Handler:
|
||||
b .
|
||||
.size SecureFault_Handler, . - SecureFault_Handler
|
||||
|
||||
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
b .
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.type DebugMon_Handler, %function
|
||||
DebugMon_Handler:
|
||||
b .
|
||||
.size DebugMon_Handler, . - DebugMon_Handler
|
||||
|
||||
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
b .
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
b .
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* IRQ Handlers */
|
||||
|
||||
.globl Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
.macro IRQ handler
|
||||
.weak \handler
|
||||
.set \handler, Default_Handler
|
||||
.endm
|
||||
|
||||
IRQ SPU_IRQHandler
|
||||
IRQ CLOCK_POWER_IRQHandler
|
||||
IRQ UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
|
||||
IRQ UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
|
||||
IRQ UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
|
||||
IRQ UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
|
||||
IRQ GPIOTE0_IRQHandler
|
||||
IRQ SAADC_IRQHandler
|
||||
IRQ TIMER0_IRQHandler
|
||||
IRQ TIMER1_IRQHandler
|
||||
IRQ TIMER2_IRQHandler
|
||||
IRQ RTC0_IRQHandler
|
||||
IRQ RTC1_IRQHandler
|
||||
IRQ WDT_IRQHandler
|
||||
IRQ EGU0_IRQHandler
|
||||
IRQ EGU1_IRQHandler
|
||||
IRQ EGU2_IRQHandler
|
||||
IRQ EGU3_IRQHandler
|
||||
IRQ EGU4_IRQHandler
|
||||
IRQ EGU5_IRQHandler
|
||||
IRQ PWM0_IRQHandler
|
||||
IRQ PWM1_IRQHandler
|
||||
IRQ PWM2_IRQHandler
|
||||
IRQ PWM3_IRQHandler
|
||||
IRQ PDM_IRQHandler
|
||||
IRQ I2S_IRQHandler
|
||||
IRQ IPC_IRQHandler
|
||||
IRQ FPU_IRQHandler
|
||||
IRQ GPIOTE1_IRQHandler
|
||||
IRQ KMU_IRQHandler
|
||||
IRQ CRYPTOCELL_IRQHandler
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,310 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UART0_IRQHandler
|
||||
DCD SPI0_TWI0_IRQHandler
|
||||
DCD SPI1_TWI1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD ADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD LPCOMP_IRQHandler
|
||||
DCD SWI0_IRQHandler
|
||||
DCD SWI1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD SWI4_IRQHandler
|
||||
DCD SWI5_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
|
||||
NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address
|
||||
NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
|
||||
|
||||
LDR R0, =NRF_POWER_RAMON_ADDRESS
|
||||
LDR R2, [R0]
|
||||
ORRS R2, R2, R1
|
||||
STR R2, [R0]
|
||||
|
||||
LDR R0, =NRF_POWER_RAMONB_ADDRESS
|
||||
LDR R2, [R0]
|
||||
ORRS R2, R2, R1
|
||||
STR R2, [R0]
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK LPCOMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LPCOMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,456 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK NFCT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NFCT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_LPCOMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_LPCOMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_EGU2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_EGU2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_EGU3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_EGU3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_EGU4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_EGU4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_EGU5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_EGU5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK MWU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MWU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2S_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,391 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD TWIM0_TWIS0_TWI0_IRQHandler
|
||||
DCD SPIM0_SPIS0_SPI0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD SWI4_IRQHandler
|
||||
DCD SWI5_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TWIM0_TWIS0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TWIM0_TWIS0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_SPI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_SPI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,429 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD TWIM0_TWIS0_TWI0_IRQHandler
|
||||
DCD SPIM0_SPIS0_SPI0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD SWI4_IRQHandler
|
||||
DCD SWI5_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
/* Workaround for Errata 185 RAM: RAM corruption at extreme corners
|
||||
* found at the Errata document for your device located
|
||||
* at https://infocenter.nordicsemi.com/index.jsp */
|
||||
|
||||
LDR R0, =0x10000130
|
||||
LDR R0, [R0]
|
||||
LDR R1, =0x10000134
|
||||
LDR R1, [R1]
|
||||
|
||||
CMP R0, #0xA
|
||||
BNE skip
|
||||
CMP R1, #0x0
|
||||
BNE skip
|
||||
|
||||
LDR R0, =0x40000EE4
|
||||
LDR R2, [R0]
|
||||
LDR R3, =0xFFFFFF8F
|
||||
ANDS R2, R2, R3
|
||||
LDR R3, =0x00000040
|
||||
ORRS R2, R2, R3
|
||||
STR R2, [R0]
|
||||
|
||||
skip
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TWIM0_TWIS0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TWIM0_TWIS0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_SPI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_SPI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,406 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
DCD SPIM0_SPIS0_SPI0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD SWI4_IRQHandler
|
||||
DCD SWI5_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_SPI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_SPI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,401 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USBD_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_EGU2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_EGU2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_EGU3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_EGU3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_EGU4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_EGU4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_EGU5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_EGU5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK USBD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBD_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,476 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD UARTE1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SPIM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK NFCT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NFCT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_LPCOMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_LPCOMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_EGU2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_EGU2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_EGU3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_EGU3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_EGU4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_EGU4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_EGU5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_EGU5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK MWU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MWU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2S_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK USBD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBD_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM3_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,486 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler
|
||||
DCD RADIO_IRQHandler
|
||||
DCD UARTE0_UART0_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
DCD NFCT_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD CCM_AAR_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD QDEC_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD SWI0_EGU0_IRQHandler
|
||||
DCD SWI1_EGU1_IRQHandler
|
||||
DCD SWI2_EGU2_IRQHandler
|
||||
DCD SWI3_EGU3_IRQHandler
|
||||
DCD SWI4_EGU4_IRQHandler
|
||||
DCD SWI5_EGU5_IRQHandler
|
||||
DCD TIMER3_IRQHandler
|
||||
DCD TIMER4_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD MWU_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD SPIM2_SPIS2_SPI2_IRQHandler
|
||||
DCD RTC2_IRQHandler
|
||||
DCD I2S_IRQHandler
|
||||
DCD FPU_IRQHandler
|
||||
DCD USBD_IRQHandler
|
||||
DCD UARTE1_IRQHandler
|
||||
DCD QSPI_IRQHandler
|
||||
DCD CRYPTOCELL_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SPIM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_UART0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK NFCT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NFCT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_LPCOMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_LPCOMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_EGU2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_EGU2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_EGU3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_EGU3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI4_EGU4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_EGU4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI5_EGU5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_EGU5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK MWU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MWU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM2_SPIS2_SPI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2S_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK USBD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBD_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QSPI_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QSPI_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CRYPTOCELL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CRYPTOCELL_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM3_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,609 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD SecureFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD FPU_IRQHandler
|
||||
DCD CACHE_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD SPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD CLOCK_POWER_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
|
||||
DCD SPIM4_IRQHandler
|
||||
DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
|
||||
DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
|
||||
DCD GPIOTE0_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC0_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD WDT0_IRQHandler
|
||||
DCD WDT1_IRQHandler
|
||||
DCD COMP_LPCOMP_IRQHandler
|
||||
DCD EGU0_IRQHandler
|
||||
DCD EGU1_IRQHandler
|
||||
DCD EGU2_IRQHandler
|
||||
DCD EGU3_IRQHandler
|
||||
DCD EGU4_IRQHandler
|
||||
DCD EGU5_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD PDM0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD I2S0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD IPC_IRQHandler
|
||||
DCD QSPI_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD NFCT_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD QDEC0_IRQHandler
|
||||
DCD QDEC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD USBD_IRQHandler
|
||||
DCD USBREGULATOR_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD KMU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CRYPTOCELL_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SecureFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SecureFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CACHE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CACHE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CLOCK_POWER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CLOCK_POWER_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK COMP_LPCOMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
COMP_LPCOMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PDM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK I2S0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2S0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK IPC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
IPC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QSPI_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QSPI_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK NFCT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NFCT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK QDEC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK USBD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBD_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK USBREGULATOR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBREGULATOR_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK KMU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
KMU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CRYPTOCELL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CRYPTOCELL_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,388 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CLOCK_POWER_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD RADIO_IRQHandler
|
||||
DCD RNG_IRQHandler
|
||||
DCD GPIOTE_IRQHandler
|
||||
DCD WDT_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD ECB_IRQHandler
|
||||
DCD AAR_CCM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD TEMP_IRQHandler
|
||||
DCD RTC0_IRQHandler
|
||||
DCD IPC_IRQHandler
|
||||
DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
DCD EGU0_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD SWI0_IRQHandler
|
||||
DCD SWI1_IRQHandler
|
||||
DCD SWI2_IRQHandler
|
||||
DCD SWI3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK CLOCK_POWER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CLOCK_POWER_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK AAR_CCM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
AAR_CCM_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK IPC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
IPC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SWI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,559 @@
|
||||
; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
|
||||
;
|
||||
; SPDX-License-Identifier: Apache-2.0
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;
|
||||
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
|
||||
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
#if defined(__STARTUP_CONFIG)
|
||||
|
||||
#include "startup_config.h"
|
||||
|
||||
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
|
||||
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
|
||||
#endif
|
||||
|
||||
SECTION CSTACK:DATA:NOROOT(__STARTUP_CONFIG_STACK_ALIGNEMENT)
|
||||
DS8 __STARTUP_CONFIG_STACK_SIZE
|
||||
|
||||
SECTION HEAP:DATA:NOROOT(3)
|
||||
DS8 __STARTUP_CONFIG_HEAP_SIZE
|
||||
|
||||
#else
|
||||
|
||||
;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD MemoryManagement_Handler
|
||||
DCD BusFault_Handler
|
||||
DCD UsageFault_Handler
|
||||
DCD SecureFault_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler
|
||||
DCD DebugMon_Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD CLOCK_POWER_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
|
||||
DCD UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
|
||||
DCD UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
|
||||
DCD UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE0_IRQHandler
|
||||
DCD SAADC_IRQHandler
|
||||
DCD TIMER0_IRQHandler
|
||||
DCD TIMER1_IRQHandler
|
||||
DCD TIMER2_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD RTC0_IRQHandler
|
||||
DCD RTC1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD WDT_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD EGU0_IRQHandler
|
||||
DCD EGU1_IRQHandler
|
||||
DCD EGU2_IRQHandler
|
||||
DCD EGU3_IRQHandler
|
||||
DCD EGU4_IRQHandler
|
||||
DCD EGU5_IRQHandler
|
||||
DCD PWM0_IRQHandler
|
||||
DCD PWM1_IRQHandler
|
||||
DCD PWM2_IRQHandler
|
||||
DCD PWM3_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD PDM_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD I2S_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD IPC_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD FPU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD GPIOTE1_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD KMU_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CRYPTOCELL_IRQHandler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK MemoryManagement_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemoryManagement_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SecureFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SecureFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK SPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CLOCK_POWER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CLOCK_POWER_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK SAADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAADC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU4_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK EGU5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EGU5_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM0_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM2_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PWM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PWM3_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK PDM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PDM_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2S_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK IPC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
IPC_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK GPIOTE1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE1_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK KMU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
KMU_IRQHandler
|
||||
B .
|
||||
|
||||
PUBWEAK CRYPTOCELL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CRYPTOCELL_IRQHandler
|
||||
B .
|
||||
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,198 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF_H
|
||||
#define NRF_H
|
||||
|
||||
/* MDK version */
|
||||
#define MDK_MAJOR_VERSION 8
|
||||
#define MDK_MINOR_VERSION 40
|
||||
#define MDK_MICRO_VERSION 3
|
||||
|
||||
|
||||
/* Define coprocessor domains */
|
||||
#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK)
|
||||
#ifndef NRF5340_XXAA
|
||||
#define NRF5340_XXAA
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA_APPLICATION)
|
||||
#ifndef NRF_APPLICATION
|
||||
#define NRF_APPLICATION
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF5340_XXAA_NETWORK)
|
||||
#ifndef NRF_NETWORK
|
||||
#define NRF_NETWORK
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Apply compatibility macros for old nRF5340 macros */
|
||||
#if defined(NRF5340_XXAA)
|
||||
#if defined (NRF_APPLICATION)
|
||||
#ifndef NRF5340_XXAA_APPLICATION
|
||||
#define NRF5340_XXAA_APPLICATION
|
||||
#endif
|
||||
#endif
|
||||
#if defined (NRF_NETWORK)
|
||||
#ifndef NRF5340_XXAA_NETWORK
|
||||
#define NRF5340_XXAA_NETWORK
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */
|
||||
#if defined (NRF51) ||\
|
||||
defined (NRF51422_XXAA) ||\
|
||||
defined (NRF51422_XXAB) ||\
|
||||
defined (NRF51422_XXAC) ||\
|
||||
defined (NRF51801_XXAB) ||\
|
||||
defined (NRF51802_XXAA) ||\
|
||||
defined (NRF51822_XXAA) ||\
|
||||
defined (NRF51822_XXAB) ||\
|
||||
defined (NRF51822_XXAC) ||\
|
||||
defined (NRF51824_XXAA)
|
||||
#ifndef NRF51_SERIES
|
||||
#define NRF51_SERIES
|
||||
#endif
|
||||
#ifndef NRF51
|
||||
#define NRF51
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
|
||||
#if defined (NRF52)
|
||||
#ifndef NRF52832_XXAA
|
||||
#define NRF52832_XXAA
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */
|
||||
#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA)
|
||||
#ifndef NRF52_SERIES
|
||||
#define NRF52_SERIES
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Define NRF53_SERIES for common use in nRF53 series devices. */
|
||||
#if defined (NRF5340_XXAA)
|
||||
#ifndef NRF53_SERIES
|
||||
#define NRF53_SERIES
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Define NRF91_SERIES for common use in nRF91 series devices. */
|
||||
#if defined (NRF9160_XXAA)
|
||||
#ifndef NRF91_SERIES
|
||||
#define NRF91_SERIES
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Device selection for device includes. */
|
||||
#if defined (NRF51)
|
||||
#include "nrf51.h"
|
||||
#include "nrf51_bitfields.h"
|
||||
#include "nrf51_deprecated.h"
|
||||
|
||||
#elif defined (NRF52805_XXAA)
|
||||
#include "nrf52805.h"
|
||||
#include "nrf52805_bitfields.h"
|
||||
#include "nrf51_to_nrf52810.h"
|
||||
#include "nrf52_to_nrf52810.h"
|
||||
#include "nrf52810_to_nrf52811.h"
|
||||
#elif defined (NRF52810_XXAA)
|
||||
#include "nrf52810.h"
|
||||
#include "nrf52810_bitfields.h"
|
||||
#include "nrf51_to_nrf52810.h"
|
||||
#include "nrf52_to_nrf52810.h"
|
||||
#include "nrf52810_name_change.h"
|
||||
#elif defined (NRF52811_XXAA)
|
||||
#include "nrf52811.h"
|
||||
#include "nrf52811_bitfields.h"
|
||||
#include "nrf51_to_nrf52810.h"
|
||||
#include "nrf52_to_nrf52810.h"
|
||||
#include "nrf52810_to_nrf52811.h"
|
||||
#elif defined (NRF52820_XXAA)
|
||||
#include "nrf52820.h"
|
||||
#include "nrf52820_bitfields.h"
|
||||
#include "nrf51_to_nrf52.h"
|
||||
#include "nrf52_to_nrf52833.h"
|
||||
#include "nrf52833_to_nrf52820.h"
|
||||
#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
|
||||
#include "nrf52.h"
|
||||
#include "nrf52_bitfields.h"
|
||||
#include "nrf51_to_nrf52.h"
|
||||
#include "nrf52_name_change.h"
|
||||
#elif defined (NRF52833_XXAA)
|
||||
#include "nrf52833.h"
|
||||
#include "nrf52833_bitfields.h"
|
||||
#include "nrf52_to_nrf52833.h"
|
||||
#include "nrf51_to_nrf52.h"
|
||||
#elif defined (NRF52840_XXAA)
|
||||
#include "nrf52840.h"
|
||||
#include "nrf52840_bitfields.h"
|
||||
#include "nrf51_to_nrf52840.h"
|
||||
#include "nrf52_to_nrf52840.h"
|
||||
|
||||
#elif defined (NRF5340_XXAA)
|
||||
#if defined(NRF_APPLICATION)
|
||||
#include "nrf5340_application.h"
|
||||
#include "nrf5340_application_bitfields.h"
|
||||
#include "nrf5340_application_name_change.h"
|
||||
#elif defined (NRF_NETWORK)
|
||||
#include "nrf5340_network.h"
|
||||
#include "nrf5340_network_bitfields.h"
|
||||
#include "nrf5340_network_name_change.h"
|
||||
#endif
|
||||
|
||||
#elif defined (NRF9160_XXAA)
|
||||
#include "nrf9160.h"
|
||||
#include "nrf9160_bitfields.h"
|
||||
#include "nrf9160_name_change.h"
|
||||
|
||||
#else
|
||||
#error "Device must be defined. See nrf.h."
|
||||
#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */
|
||||
|
||||
#include "compiler_abstraction.h"
|
||||
|
||||
#endif /* NRF_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,177 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
/* This file is deprecated */
|
||||
#ifndef _NRF51422_PERIPHERALS_H
|
||||
#define _NRF51422_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 64
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 8
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 16
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 4
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 16
|
||||
#define TIMER2_MAX_SIZE 16
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA */
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Analog to Digital Converter */
|
||||
#define ADC_PRESENT
|
||||
#define ADC_COUNT 1
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 4
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 8
|
||||
|
||||
|
||||
#endif // _NRF51422_PERIPHERALS_H
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,177 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
/* This file is deprecated */
|
||||
#ifndef _NRF51801_PERIPHERALS_H
|
||||
#define _NRF51801_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 64
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 8
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 16
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 4
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 16
|
||||
#define TIMER2_MAX_SIZE 16
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA */
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Analog to Digital Converter */
|
||||
#define ADC_PRESENT
|
||||
#define ADC_COUNT 1
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 4
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 8
|
||||
|
||||
|
||||
#endif // _NRF51801_PERIPHERALS_H
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,177 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
/* This file is deprecated */
|
||||
#ifndef _NRF51802_PERIPHERALS_H
|
||||
#define _NRF51802_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 64
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 8
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 16
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 4
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 16
|
||||
#define TIMER2_MAX_SIZE 16
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA */
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Analog to Digital Converter */
|
||||
#define ADC_PRESENT
|
||||
#define ADC_COUNT 1
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 4
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 8
|
||||
|
||||
|
||||
#endif // _NRF51802_PERIPHERALS_H
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,178 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/* This file is deprecated */
|
||||
#ifndef _NRF51822_PERIPHERALS_H
|
||||
#define _NRF51822_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 64
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 8
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 16
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 4
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 16
|
||||
#define TIMER2_MAX_SIZE 16
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA */
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Analog to Digital Converter */
|
||||
#define ADC_PRESENT
|
||||
#define ADC_COUNT 1
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 4
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 8
|
||||
|
||||
|
||||
#endif // _NRF51822_PERIPHERALS_H
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,178 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/* This file is deprecated */
|
||||
#ifndef _NRF51824_PERIPHERALS_H
|
||||
#define _NRF51824_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 64
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 8
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 16
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 4
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 16
|
||||
#define TIMER2_MAX_SIZE 16
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA */
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Analog to Digital Converter */
|
||||
#define ADC_PRESENT
|
||||
#define ADC_COUNT 1
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 4
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 8
|
||||
|
||||
|
||||
#endif // _NRF51824_PERIPHERALS_H
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,171 @@
|
||||
/* Deprecated linker script for Nordic Semiconductor nRF51 devices
|
||||
* please use nrfx_common.ld. This version exists for backwards
|
||||
* compatibility.
|
||||
*
|
||||
* Version: Sourcery G++ 4.5-1
|
||||
* Support: https://support.codesourcery.com/GNUToolchain/
|
||||
*
|
||||
* Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
|
||||
*
|
||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
||||
*/
|
||||
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapBase
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__HeapBase = .;
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
KEEP(*(.heap*))
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
KEEP(*(.stack*))
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
|
||||
/* Check if text sections + data exceeds FLASH limit */
|
||||
DataInitFlashUsed = __bss_start__ - __data_start__;
|
||||
CodeFlashUsed = __etext - ORIGIN(FLASH);
|
||||
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
|
||||
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
|
||||
|
||||
}
|
||||
@@ -0,0 +1,455 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF51_DEPRECATED_H
|
||||
#define NRF51_DEPRECATED_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and
|
||||
* nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
|
||||
* macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
|
||||
*/
|
||||
|
||||
/* NVMC */
|
||||
/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
|
||||
#define ERASEPROTECTEDPAGE ERASEPCR0
|
||||
|
||||
|
||||
/* LPCOMP */
|
||||
/* The interrupt ISR was renamed. Adding old name to the macros. */
|
||||
#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler
|
||||
#define LPCOMP_COMP_IRQn LPCOMP_IRQn
|
||||
/* Corrected typo in RESULT register. */
|
||||
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
|
||||
|
||||
|
||||
/* MPU */
|
||||
/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
|
||||
#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos
|
||||
#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk
|
||||
#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1
|
||||
#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0
|
||||
|
||||
|
||||
/* POWER */
|
||||
/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
|
||||
#define POWER_RAMON_OFFRAM3_Pos (19UL)
|
||||
#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos)
|
||||
#define POWER_RAMON_OFFRAM3_RAM3Off (0UL)
|
||||
#define POWER_RAMON_OFFRAM3_RAM3On (1UL)
|
||||
/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
|
||||
#define POWER_RAMON_OFFRAM2_Pos (18UL)
|
||||
#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos)
|
||||
#define POWER_RAMON_OFFRAM2_RAM2Off (0UL)
|
||||
#define POWER_RAMON_OFFRAM2_RAM2On (1UL)
|
||||
/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
|
||||
#define POWER_RAMON_ONRAM3_Pos (3UL)
|
||||
#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos)
|
||||
#define POWER_RAMON_ONRAM3_RAM3Off (0UL)
|
||||
#define POWER_RAMON_ONRAM3_RAM3On (1UL)
|
||||
/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
|
||||
#define POWER_RAMON_ONRAM2_Pos (2UL)
|
||||
#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos)
|
||||
#define POWER_RAMON_ONRAM2_RAM2Off (0UL)
|
||||
#define POWER_RAMON_ONRAM2_RAM2On (1UL)
|
||||
|
||||
|
||||
/* RADIO */
|
||||
/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
|
||||
#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm
|
||||
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
|
||||
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
|
||||
/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos
|
||||
#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk
|
||||
#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled
|
||||
#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled
|
||||
/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
|
||||
#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos
|
||||
#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk
|
||||
#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled
|
||||
#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled
|
||||
|
||||
|
||||
/* FICR */
|
||||
/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
|
||||
#define SIZERAMBLOCK0 SIZERAMBLOCKS
|
||||
#define SIZERAMBLOCK1 SIZERAMBLOCKS
|
||||
#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
|
||||
#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
|
||||
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
|
||||
#define DEVICEID0 DEVICEID[0]
|
||||
#define DEVICEID1 DEVICEID[1]
|
||||
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
|
||||
#define ER0 ER[0]
|
||||
#define ER1 ER[1]
|
||||
#define ER2 ER[2]
|
||||
#define ER3 ER[3]
|
||||
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
|
||||
#define IR0 IR[0]
|
||||
#define IR1 IR[1]
|
||||
#define IR2 IR[2]
|
||||
#define IR3 IR[3]
|
||||
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
|
||||
#define DEVICEADDR0 DEVICEADDR[0]
|
||||
#define DEVICEADDR1 DEVICEADDR[1]
|
||||
|
||||
|
||||
/* PPI */
|
||||
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
|
||||
#define TASKS_CHG0EN TASKS_CHG[0].EN
|
||||
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
|
||||
#define TASKS_CHG1EN TASKS_CHG[1].EN
|
||||
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
|
||||
#define TASKS_CHG2EN TASKS_CHG[2].EN
|
||||
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
|
||||
#define TASKS_CHG3EN TASKS_CHG[3].EN
|
||||
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
|
||||
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
|
||||
#define CH0_EEP CH[0].EEP
|
||||
#define CH0_TEP CH[0].TEP
|
||||
#define CH1_EEP CH[1].EEP
|
||||
#define CH1_TEP CH[1].TEP
|
||||
#define CH2_EEP CH[2].EEP
|
||||
#define CH2_TEP CH[2].TEP
|
||||
#define CH3_EEP CH[3].EEP
|
||||
#define CH3_TEP CH[3].TEP
|
||||
#define CH4_EEP CH[4].EEP
|
||||
#define CH4_TEP CH[4].TEP
|
||||
#define CH5_EEP CH[5].EEP
|
||||
#define CH5_TEP CH[5].TEP
|
||||
#define CH6_EEP CH[6].EEP
|
||||
#define CH6_TEP CH[6].TEP
|
||||
#define CH7_EEP CH[7].EEP
|
||||
#define CH7_TEP CH[7].TEP
|
||||
#define CH8_EEP CH[8].EEP
|
||||
#define CH8_TEP CH[8].TEP
|
||||
#define CH9_EEP CH[9].EEP
|
||||
#define CH9_TEP CH[9].TEP
|
||||
#define CH10_EEP CH[10].EEP
|
||||
#define CH10_TEP CH[10].TEP
|
||||
#define CH11_EEP CH[11].EEP
|
||||
#define CH11_TEP CH[11].TEP
|
||||
#define CH12_EEP CH[12].EEP
|
||||
#define CH12_TEP CH[12].TEP
|
||||
#define CH13_EEP CH[13].EEP
|
||||
#define CH13_TEP CH[13].TEP
|
||||
#define CH14_EEP CH[14].EEP
|
||||
#define CH14_TEP CH[14].TEP
|
||||
#define CH15_EEP CH[15].EEP
|
||||
#define CH15_TEP CH[15].TEP
|
||||
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
|
||||
#define CHG0 CHG[0]
|
||||
#define CHG1 CHG[1]
|
||||
#define CHG2 CHG[2]
|
||||
#define CHG3 CHG[3]
|
||||
/* All bitfield macros for the CHGx registers therefore changed name. */
|
||||
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
|
||||
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
|
||||
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
|
||||
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
|
||||
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
|
||||
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
|
||||
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
|
||||
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
|
||||
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
|
||||
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
|
||||
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
|
||||
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
|
||||
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
|
||||
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
|
||||
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
|
||||
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
|
||||
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
|
||||
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
|
||||
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
|
||||
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
|
||||
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
|
||||
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
|
||||
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
|
||||
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
|
||||
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
|
||||
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
|
||||
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
|
||||
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
|
||||
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
|
||||
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
|
||||
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
|
||||
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
|
||||
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
|
||||
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
|
||||
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
|
||||
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
|
||||
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included
|
||||
#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included
|
||||
#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included
|
||||
#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included
|
||||
#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included
|
||||
#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included
|
||||
#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included
|
||||
#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included
|
||||
#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included
|
||||
#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included
|
||||
#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included
|
||||
#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included
|
||||
#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos
|
||||
#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk
|
||||
#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded
|
||||
#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included
|
||||
#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos
|
||||
#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk
|
||||
#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded
|
||||
#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included
|
||||
#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos
|
||||
#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk
|
||||
#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded
|
||||
#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included
|
||||
#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos
|
||||
#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk
|
||||
#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded
|
||||
#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included
|
||||
#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos
|
||||
#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk
|
||||
#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded
|
||||
#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included
|
||||
#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos
|
||||
#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk
|
||||
#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded
|
||||
#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included
|
||||
#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos
|
||||
#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk
|
||||
#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded
|
||||
#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included
|
||||
#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos
|
||||
#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk
|
||||
#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded
|
||||
#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included
|
||||
#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos
|
||||
#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk
|
||||
#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded
|
||||
#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included
|
||||
#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos
|
||||
#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk
|
||||
#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded
|
||||
#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included
|
||||
#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos
|
||||
#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk
|
||||
#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded
|
||||
#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included
|
||||
#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos
|
||||
#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk
|
||||
#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded
|
||||
#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included
|
||||
#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos
|
||||
#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk
|
||||
#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded
|
||||
#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included
|
||||
#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos
|
||||
#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk
|
||||
#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded
|
||||
#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included
|
||||
#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos
|
||||
#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk
|
||||
#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded
|
||||
#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included
|
||||
#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos
|
||||
#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk
|
||||
#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded
|
||||
#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included
|
||||
|
||||
/* SPIS */
|
||||
/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE
|
||||
|
||||
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF51_DEPRECATED_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF51_PERIPHERALS_H
|
||||
#define _NRF51_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 64
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 8
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 16
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 4
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 16
|
||||
#define TIMER2_MAX_SIZE 16
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA */
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Analog to Digital Converter */
|
||||
#define ADC_PRESENT
|
||||
#define ADC_COUNT 1
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 4
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 8
|
||||
|
||||
|
||||
#endif // _NRF51_PERIPHERALS_H
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,13 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,230 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52805_PERIPHERALS_H
|
||||
#define _NRF52805_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 48
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 10
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 2
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 1
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 14
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 14
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 1
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 1
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 1
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 1
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
#define SAADC_CH_NUM 8
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
|
||||
#endif // _NRF52805_PERIPHERALS_H
|
||||
@@ -0,0 +1,14 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x6000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x6000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF52810_NAME_CHANGE_H
|
||||
#define NRF52810_NAME_CHANGE_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the updates made to nrf52810.h and
|
||||
* nrf52810_bitfields.h. The macros defined in this file were available previously. Do not use these
|
||||
* macros on purpose. Use the ones defined in nrf52810.h and nrf52810_bitfields.h instead.
|
||||
*/
|
||||
|
||||
/* IRQ */
|
||||
/* Changes of interrupt names */
|
||||
#define SPIM0_SPIS0_IRQn SPIM0_SPIS0_SPI0_IRQn
|
||||
#define TWIM0_TWIS0_IRQn TWIM0_TWIS0_TWI0_IRQn
|
||||
#define UARTE0_IRQn UARTE0_UART0_IRQn
|
||||
|
||||
#define SPIM0_SPIS0_IRQHandler SPIM0_SPIS0_SPI0_IRQHandler
|
||||
#define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_TWI0_IRQHandler
|
||||
#define UARTE0_IRQHandler UARTE0_UART0_IRQHandler
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF52810_NAME_CHANGE_H */
|
||||
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52810_PERIPHERALS_H
|
||||
#define _NRF52810_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 48
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 2
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 1
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 10
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 1
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 10
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 1
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 1
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 10
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 1
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 10
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 1
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 10
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
#define SAADC_CH_NUM 8
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
/* Pulse Width Modulator */
|
||||
#define PWM_PRESENT
|
||||
#define PWM_COUNT 1
|
||||
|
||||
#define PWM0_CH_NUM 4
|
||||
|
||||
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Pulse Density Modulator */
|
||||
#define PDM_PRESENT
|
||||
#define PDM_COUNT 1
|
||||
|
||||
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
|
||||
#endif // _NRF52810_PERIPHERALS_H
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF52810_TO_NRF52811_H
|
||||
#define NRF52810_TO_NRF52811_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF52810 and nRF52811 devices.
|
||||
* It redefines the old nRF52810 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. */
|
||||
|
||||
/* Differences between latest nRF52810 headers and nRF52811 headers. */
|
||||
|
||||
/* Interrupt service routines handlers. */
|
||||
#ifndef TWIM0_TWIS0_IRQHandler
|
||||
#define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
|
||||
#endif
|
||||
|
||||
|
||||
/* Interrupt service routines index. */
|
||||
#ifndef TWIM0_TWIS0_IRQn
|
||||
#define TWIM0_TWIS0_IRQn TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn
|
||||
#endif
|
||||
|
||||
/*lint --flb "Leave library region" */
|
||||
|
||||
#endif /* NRF52810_TO_NRF52811_H */
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x6000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x6000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,249 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52811_PERIPHERALS_H
|
||||
#define _NRF52811_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
#define BPROT_REGIONS_NUM 48
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 2
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 3
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 2
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 14
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 2
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 14
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 1
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 1
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 1
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 1
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
#define SAADC_CH_NUM 8
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
/* Pulse Width Modulator */
|
||||
#define PWM_PRESENT
|
||||
#define PWM_COUNT 1
|
||||
|
||||
#define PWM0_CH_NUM 4
|
||||
|
||||
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Pulse Density Modulator */
|
||||
#define PDM_PRESENT
|
||||
#define PDM_COUNT 1
|
||||
|
||||
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
|
||||
#endif // _NRF52811_PERIPHERALS_H
|
||||
@@ -0,0 +1,14 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x6000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x6000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52820_PERIPHERALS_H
|
||||
#define _NRF52820_PERIPHERALS_H
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 4
|
||||
|
||||
#define POWER_FEATURE_VDDH_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM (18)
|
||||
#define P0_FEATURE_PINS_PRESENT (nrf52_errata_230() ? 0xF0168E3Ful : 0x7017C1FFul)
|
||||
|
||||
/* ACL */
|
||||
#define ACL_PRESENT
|
||||
|
||||
#define ACL_REGIONS_COUNT 8
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 14
|
||||
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 6
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
#define EGU2_CH_NUM 16
|
||||
#define EGU3_CH_NUM 16
|
||||
#define EGU4_CH_NUM 16
|
||||
#define EGU5_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 4
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
#define TIMER3_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
#define TIMER3_CC_NUM 6
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 2
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 2
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 2
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 2
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 2
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define TWIM1_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 2
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define TWIS1_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 1
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
|
||||
/* Universal Serial Bus Device */
|
||||
#define USBD_PRESENT
|
||||
#define USBD_COUNT 1
|
||||
|
||||
#define USBD_EASYDMA_MAXCNT_SIZE 7
|
||||
|
||||
#endif // _NRF52820_PERIPHERALS_H
|
||||
@@ -0,0 +1,14 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x8000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,308 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52832_PERIPHERALS_H
|
||||
#define _NRF52832_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#if defined(NRF52832_XXAA)
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 8
|
||||
#elif defined(NRF52832_XXAB)
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 4
|
||||
#endif
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
#define NVMC_FEATURE_CACHE_PRESENT
|
||||
|
||||
/* Floating Point Unit */
|
||||
#define FPU_PRESENT
|
||||
#define FPU_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* Memory Watch Unit */
|
||||
#define MWU_PRESENT
|
||||
#define MWU_COUNT 1
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 1
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
|
||||
/* MPU and BPROT */
|
||||
#define BPROT_PRESENT
|
||||
|
||||
#define BPROT_REGIONS_SIZE 4096
|
||||
|
||||
#if defined(NRF52832_XXAA)
|
||||
#define BPROT_REGIONS_NUM 128
|
||||
#elif defined(NRF52832_XXAB)
|
||||
#define BPROT_REGIONS_NUM 64
|
||||
#endif
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* NFC Tag */
|
||||
#define NFCT_PRESENT
|
||||
#define NFCT_COUNT 1
|
||||
|
||||
#define NFCT_EASYDMA_MAXCNT_SIZE 9
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 6
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
#define EGU2_CH_NUM 16
|
||||
#define EGU3_CH_NUM 16
|
||||
#define EGU4_CH_NUM 16
|
||||
#define EGU5_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 5
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
#define TIMER3_MAX_SIZE 32
|
||||
#define TIMER4_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
#define TIMER3_CC_NUM 6
|
||||
#define TIMER4_CC_NUM 6
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 3
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
#define RTC2_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 3
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 3
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
#define SPIM2_MAX_DATARATE 8
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM2_FEATURE_DCX_PRESENT 0
|
||||
|
||||
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIM2_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 3
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
#define SPIS2_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 2
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define TWIM1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 2
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 8
|
||||
#define TWIS1_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 1
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 8
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
#define SAADC_CH_NUM 8
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 16
|
||||
|
||||
#define LPCOMP_FEATURE_HYST_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
/* Pulse Width Modulator */
|
||||
#define PWM_PRESENT
|
||||
#define PWM_COUNT 3
|
||||
|
||||
#define PWM0_CH_NUM 4
|
||||
#define PWM1_CH_NUM 4
|
||||
#define PWM2_CH_NUM 4
|
||||
|
||||
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM1_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM2_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Pulse Density Modulator */
|
||||
#define PDM_PRESENT
|
||||
#define PDM_COUNT 1
|
||||
|
||||
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Inter-IC Sound Interface */
|
||||
#define I2S_PRESENT
|
||||
#define I2S_COUNT 1
|
||||
|
||||
#define I2S_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
|
||||
#endif // _NRF52832_PERIPHERALS_H
|
||||
@@ -0,0 +1,14 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x10000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
@@ -0,0 +1,14 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x8000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,322 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52833_PERIPHERALS_H
|
||||
#define _NRF52833_PERIPHERALS_H
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
#define CLOCK_FEATURE_LFXO_EXTENDED_DEBOUNCE_PRESENT
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
|
||||
|
||||
#define POWER_FEATURE_VDDH_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
#define NVMC_FEATURE_CACHE_PRESENT
|
||||
|
||||
/* Floating Point Unit */
|
||||
#define FPU_PRESENT
|
||||
#define FPU_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* Memory Watch Unit */
|
||||
#define MWU_PRESENT
|
||||
#define MWU_COUNT 1
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 2
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
#define P1_PIN_NUM 10
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
#define P1_FEATURE_PINS_PRESENT 0x000003FFUL
|
||||
|
||||
/* ACL */
|
||||
#define ACL_PRESENT
|
||||
|
||||
#define ACL_REGIONS_COUNT 8
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* NFC Tag */
|
||||
#define NFCT_PRESENT
|
||||
#define NFCT_COUNT 1
|
||||
|
||||
#define NFCT_EASYDMA_MAXCNT_SIZE 9
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 6
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
#define EGU2_CH_NUM 16
|
||||
#define EGU3_CH_NUM 16
|
||||
#define EGU4_CH_NUM 16
|
||||
#define EGU5_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 5
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
#define TIMER3_MAX_SIZE 32
|
||||
#define TIMER4_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
#define TIMER3_CC_NUM 6
|
||||
#define TIMER4_CC_NUM 6
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 3
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
#define RTC2_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 3
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 4
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
#define SPIM2_MAX_DATARATE 8
|
||||
#define SPIM3_MAX_DATARATE 32
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
|
||||
|
||||
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM2_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM3_FEATURE_DCX_PRESENT 1
|
||||
|
||||
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM3_FEATURE_RXDELAY_PRESENT 1
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 3
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 2
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 2
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
#define UART0_FEATURE_ODD_PARITY_PRESENT
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 2
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
#define UARTE0_FEATURE_ODD_PARITY_PRESENT
|
||||
#define UARTE1_FEATURE_ODD_PARITY_PRESENT
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
#define SAADC_CH_NUM 8
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 16
|
||||
|
||||
#define LPCOMP_FEATURE_HYST_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
/* Pulse Width Modulator */
|
||||
#define PWM_PRESENT
|
||||
#define PWM_COUNT 4
|
||||
|
||||
#define PWM0_CH_NUM 4
|
||||
#define PWM1_CH_NUM 4
|
||||
#define PWM2_CH_NUM 4
|
||||
#define PWM3_CH_NUM 4
|
||||
|
||||
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM1_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM2_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM3_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Pulse Density Modulator */
|
||||
#define PDM_PRESENT
|
||||
#define PDM_COUNT 1
|
||||
|
||||
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Inter-IC Sound Interface */
|
||||
#define I2S_PRESENT
|
||||
#define I2S_COUNT 1
|
||||
|
||||
#define I2S_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Universal Serial Bus Device */
|
||||
#define USBD_PRESENT
|
||||
#define USBD_COUNT 1
|
||||
|
||||
#define USBD_EASYDMA_MAXCNT_SIZE 7
|
||||
|
||||
#endif // _NRF52833_PERIPHERALS_H
|
||||
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef NRF52833_TO_NRF52820_H
|
||||
#define NRF52833_TO_NRF52820_H
|
||||
|
||||
/*lint ++flb "Enter library region */
|
||||
|
||||
/* This file is given to prevent your SW from not compiling with the name changes between nRF52833 and nRF52820 devices.
|
||||
* It redefines the old nRF52833 names into the new ones as long as the functionality is still supported. If the
|
||||
* functionality is gone, there old names are not defined, so compilation will fail. */
|
||||
|
||||
/* Differences between latest nRF52833 headers and nRF52820 headers. */
|
||||
|
||||
#endif /* NRF52833_TO_NRF52820_H */
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x20000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,327 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2010 - 2021, Nordic Semiconductor ASA
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form, except as embedded into a Nordic
|
||||
Semiconductor ASA integrated circuit in a product or a software update for
|
||||
such product, must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in the documentation and/or other
|
||||
materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||
contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
4. This software, with or without modification, must only be used with a
|
||||
Nordic Semiconductor ASA integrated circuit.
|
||||
|
||||
5. Any software provided in binary form under this license must not be reverse
|
||||
engineered, decompiled, modified and/or disassembled.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
|
||||
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NRF52840_PERIPHERALS_H
|
||||
#define _NRF52840_PERIPHERALS_H
|
||||
|
||||
|
||||
/* Clock Peripheral */
|
||||
#define CLOCK_PRESENT
|
||||
#define CLOCK_COUNT 1
|
||||
|
||||
/* Power Peripheral */
|
||||
#define POWER_PRESENT
|
||||
#define POWER_COUNT 1
|
||||
|
||||
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
|
||||
|
||||
#define POWER_FEATURE_VDDH_PRESENT
|
||||
#define POWER_FEATURE_VDDH_DCDC_PRESENT
|
||||
|
||||
/* Non-Volatile Memory Controller */
|
||||
#define NVMC_PRESENT
|
||||
#define NVMC_COUNT 1
|
||||
|
||||
#define NVMC_FEATURE_CACHE_PRESENT
|
||||
|
||||
/* Floating Point Unit */
|
||||
#define FPU_PRESENT
|
||||
#define FPU_COUNT 1
|
||||
|
||||
/* Systick timer */
|
||||
#define SYSTICK_PRESENT
|
||||
#define SYSTICK_COUNT 1
|
||||
|
||||
/* Software Interrupts */
|
||||
#define SWI_PRESENT
|
||||
#define SWI_COUNT 6
|
||||
|
||||
/* Memory Watch Unit */
|
||||
#define MWU_PRESENT
|
||||
#define MWU_COUNT 1
|
||||
|
||||
/* GPIO */
|
||||
#define GPIO_PRESENT
|
||||
#define GPIO_COUNT 2
|
||||
|
||||
#define P0_PIN_NUM 32
|
||||
#define P1_PIN_NUM 16
|
||||
|
||||
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||
#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL
|
||||
|
||||
/* ACL */
|
||||
#define ACL_PRESENT
|
||||
|
||||
#define ACL_REGIONS_COUNT 8
|
||||
|
||||
/* Radio */
|
||||
#define RADIO_PRESENT
|
||||
#define RADIO_COUNT 1
|
||||
|
||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||
|
||||
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
|
||||
|
||||
/* Accelerated Address Resolver */
|
||||
#define AAR_PRESENT
|
||||
#define AAR_COUNT 1
|
||||
|
||||
#define AAR_MAX_IRK_NUM 16
|
||||
|
||||
/* AES Electronic CodeBook mode encryption */
|
||||
#define ECB_PRESENT
|
||||
#define ECB_COUNT 1
|
||||
|
||||
/* AES CCM mode encryption */
|
||||
#define CCM_PRESENT
|
||||
#define CCM_COUNT 1
|
||||
|
||||
/* NFC Tag */
|
||||
#define NFCT_PRESENT
|
||||
#define NFCT_COUNT 1
|
||||
|
||||
#define NFCT_EASYDMA_MAXCNT_SIZE 9
|
||||
|
||||
/* Peripheral to Peripheral Interconnect */
|
||||
#define PPI_PRESENT
|
||||
#define PPI_COUNT 1
|
||||
|
||||
#define PPI_CH_NUM 20
|
||||
#define PPI_FIXED_CH_NUM 12
|
||||
#define PPI_GROUP_NUM 6
|
||||
#define PPI_FEATURE_FORKS_PRESENT
|
||||
|
||||
/* Event Generator Unit */
|
||||
#define EGU_PRESENT
|
||||
#define EGU_COUNT 6
|
||||
|
||||
#define EGU0_CH_NUM 16
|
||||
#define EGU1_CH_NUM 16
|
||||
#define EGU2_CH_NUM 16
|
||||
#define EGU3_CH_NUM 16
|
||||
#define EGU4_CH_NUM 16
|
||||
#define EGU5_CH_NUM 16
|
||||
|
||||
/* Timer/Counter */
|
||||
#define TIMER_PRESENT
|
||||
#define TIMER_COUNT 5
|
||||
|
||||
#define TIMER0_MAX_SIZE 32
|
||||
#define TIMER1_MAX_SIZE 32
|
||||
#define TIMER2_MAX_SIZE 32
|
||||
#define TIMER3_MAX_SIZE 32
|
||||
#define TIMER4_MAX_SIZE 32
|
||||
|
||||
#define TIMER0_CC_NUM 4
|
||||
#define TIMER1_CC_NUM 4
|
||||
#define TIMER2_CC_NUM 4
|
||||
#define TIMER3_CC_NUM 6
|
||||
#define TIMER4_CC_NUM 6
|
||||
|
||||
/* Real Time Counter */
|
||||
#define RTC_PRESENT
|
||||
#define RTC_COUNT 3
|
||||
|
||||
#define RTC0_CC_NUM 3
|
||||
#define RTC1_CC_NUM 4
|
||||
#define RTC2_CC_NUM 4
|
||||
|
||||
/* RNG */
|
||||
#define RNG_PRESENT
|
||||
#define RNG_COUNT 1
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_PRESENT
|
||||
#define WDT_COUNT 1
|
||||
|
||||
/* Temperature Sensor */
|
||||
#define TEMP_PRESENT
|
||||
#define TEMP_COUNT 1
|
||||
|
||||
/* Serial Peripheral Interface Master */
|
||||
#define SPI_PRESENT
|
||||
#define SPI_COUNT 3
|
||||
|
||||
/* Serial Peripheral Interface Master with DMA */
|
||||
#define SPIM_PRESENT
|
||||
#define SPIM_COUNT 4
|
||||
|
||||
#define SPIM0_MAX_DATARATE 8
|
||||
#define SPIM1_MAX_DATARATE 8
|
||||
#define SPIM2_MAX_DATARATE 8
|
||||
#define SPIM3_MAX_DATARATE 32
|
||||
|
||||
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
|
||||
|
||||
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM2_FEATURE_DCX_PRESENT 0
|
||||
#define SPIM3_FEATURE_DCX_PRESENT 1
|
||||
|
||||
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
|
||||
#define SPIM3_FEATURE_RXDELAY_PRESENT 1
|
||||
|
||||
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Serial Peripheral Interface Slave with DMA*/
|
||||
#define SPIS_PRESENT
|
||||
#define SPIS_COUNT 3
|
||||
|
||||
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
|
||||
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Two Wire Interface Master */
|
||||
#define TWI_PRESENT
|
||||
#define TWI_COUNT 2
|
||||
|
||||
/* Two Wire Interface Master with DMA */
|
||||
#define TWIM_PRESENT
|
||||
#define TWIM_COUNT 2
|
||||
|
||||
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Two Wire Interface Slave with DMA */
|
||||
#define TWIS_PRESENT
|
||||
#define TWIS_COUNT 2
|
||||
|
||||
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter */
|
||||
#define UART_PRESENT
|
||||
#define UART_COUNT 1
|
||||
|
||||
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||
#define UARTE_PRESENT
|
||||
#define UARTE_COUNT 2
|
||||
|
||||
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
|
||||
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
|
||||
|
||||
/* Quadrature Decoder */
|
||||
#define QDEC_PRESENT
|
||||
#define QDEC_COUNT 1
|
||||
|
||||
/* Successive Approximation Analog to Digital Converter */
|
||||
#define SAADC_PRESENT
|
||||
#define SAADC_COUNT 1
|
||||
|
||||
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
#define SAADC_CH_NUM 8
|
||||
|
||||
/* GPIO Tasks and Events */
|
||||
#define GPIOTE_PRESENT
|
||||
#define GPIOTE_COUNT 1
|
||||
|
||||
#define GPIOTE_CH_NUM 8
|
||||
|
||||
#define GPIOTE_FEATURE_SET_PRESENT
|
||||
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||
|
||||
/* Low Power Comparator */
|
||||
#define LPCOMP_PRESENT
|
||||
#define LPCOMP_COUNT 1
|
||||
|
||||
#define LPCOMP_REFSEL_RESOLUTION 16
|
||||
|
||||
#define LPCOMP_FEATURE_HYST_PRESENT
|
||||
|
||||
/* Comparator */
|
||||
#define COMP_PRESENT
|
||||
#define COMP_COUNT 1
|
||||
|
||||
/* Pulse Width Modulator */
|
||||
#define PWM_PRESENT
|
||||
#define PWM_COUNT 4
|
||||
|
||||
#define PWM0_CH_NUM 4
|
||||
#define PWM1_CH_NUM 4
|
||||
#define PWM2_CH_NUM 4
|
||||
#define PWM3_CH_NUM 4
|
||||
|
||||
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM1_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM2_EASYDMA_MAXCNT_SIZE 15
|
||||
#define PWM3_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Pulse Density Modulator */
|
||||
#define PDM_PRESENT
|
||||
#define PDM_COUNT 1
|
||||
|
||||
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||
|
||||
/* Inter-IC Sound Interface */
|
||||
#define I2S_PRESENT
|
||||
#define I2S_COUNT 1
|
||||
|
||||
#define I2S_EASYDMA_MAXCNT_SIZE 14
|
||||
|
||||
/* Universal Serial Bus Device */
|
||||
#define USBD_PRESENT
|
||||
#define USBD_COUNT 1
|
||||
|
||||
#define USBD_EASYDMA_MAXCNT_SIZE 7
|
||||
|
||||
/* ARM TrustZone Cryptocell 310 */
|
||||
#define CRYPTOCELL_PRESENT
|
||||
#define CRYPTOCELL_COUNT 1
|
||||
|
||||
/* Quad SPI */
|
||||
#define QSPI_PRESENT
|
||||
#define QSPI_COUNT 1
|
||||
|
||||
#define QSPI_EASYDMA_MAXCNT_SIZE 20
|
||||
|
||||
#endif // _NRF52840_PERIPHERALS_H
|
||||
@@ -0,0 +1,15 @@
|
||||
/* Linker script to configure memory regions. */
|
||||
|
||||
SEARCH_DIR(.)
|
||||
GROUP(-lgcc -lc -lnosys)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000
|
||||
EXTFLASH (rx) : ORIGIN = 0x12000000, LENGTH = 0x8000000
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
|
||||
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x40000
|
||||
}
|
||||
|
||||
|
||||
INCLUDE "nrf_common.ld"
|
||||
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Reference in New Issue
Block a user