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Initial commit: MT firmware project

Browse Source 
- BLE peripheral applications
- dr_piezo and bladder_patch projects

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
This commit is contained in:
Charles Kwon
2026-01-25 17:26:39 +09:00
commit a8ba31871e
2561 changed files with 1594625 additions and 0 deletions
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project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/Auto_FcArm_Cmd.inp
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..\..\..\..\..\..\..\pc_firm\dr_adc121s051\dr_adc121s051.c,
..\..\..\..\..\..\..\pc_firm\dr_adc121s051\dr_adc121s051.h
TO nrf52840_xxaa.hex RTE NOPRINT
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/EventRecorderStub.scvd
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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/JLinkLog.txt
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T17578 000:016.299 SEGGER J-Link V7.22b Log File
T17578 000:016.864 DLL Compiled: Jun 17 2021 17:22:49
T17578 000:016.869 Logging started @ 2026-01-24 07:30
T17578 000:016.873 - 16.875ms
T17578 000:017.062 JLINK_SetWarnOutHandler(...)
T17578 000:017.200 - 0.139ms
T17578 000:017.206 JLINK_OpenEx(...)
T17578 000:021.737 Firmware: J-Link OB-SAM3U128-V2-NordicSemi compiled Jul 8 2025 10:14:41
T17578 000:021.932 Firmware: J-Link OB-SAM3U128-V2-NordicSemi compiled Jul 8 2025 10:14:41
T17578 000:023.526 Hardware: V1.00
T17578 000:023.541 S/N: 682060510
T17578 000:023.553 OEM: SEGGER
T17578 000:023.584 Feature(s): RDI, FlashBP, FlashDL, JFlash, GDB
T17578 000:024.858 TELNET listener socket opened on port 19021
T17578 000:025.175 WEBSRV Starting webserver
T17578 000:025.338 WEBSRV Webserver running on local port 19080
T17578 000:025.348 - 8.144ms returns "O.K."
T17578 000:025.367 JLINK_GetEmuCaps()
T17578 000:025.371 - 0.007ms returns 0xB8EA5A33
T17578 000:025.659 JLINK_TIF_GetAvailable(...)
T17578 000:025.792 - 0.142ms
T17578 000:025.810 JLINK_SetErrorOutHandler(...)
T17578 000:025.815 - 0.006ms
T17578 000:026.191 JLINK_ExecCommand("ProjectFile = "D:\mt_project\mt_firmware\project\ble_peripheral\ble_app_bladder_patch\pca10056\s140\arm5_no_packs\JLinkSettings.ini"", ...).
T17578 000:042.853 - 16.685ms returns 0x00
T17578 000:050.030 JLINK_ExecCommand("Device = nRF52840_xxAA", ...).
T17578 000:056.080 Device "NRF52840_XXAA" selected.
T17578 000:056.499 - 6.440ms returns 0x00
T17578 000:056.983 JLINK_GetHardwareVersion()
T17578 000:056.998 - 0.017ms returns 10000
T17578 000:057.003 JLINK_GetDLLVersion()
T17578 000:057.007 - 0.005ms returns 72202
T17578 000:057.013 JLINK_GetOEMString(...)
T17578 000:057.018 JLINK_GetFirmwareString(...)
T17578 000:057.027 - 0.011ms
T17578 000:067.210 JLINK_GetDLLVersion()
T17578 000:067.242 - 0.034ms returns 72202
T17578 000:067.248 JLINK_GetCompileDateTime()
T17578 000:067.253 - 0.006ms
T17578 000:070.610 JLINK_GetFirmwareString(...)
T17578 000:070.630 - 0.022ms
T17578 000:076.118 JLINK_GetHardwareVersion()
T17578 000:076.149 - 0.036ms returns 10000
T17578 000:081.686 JLINK_GetSN()
T17578 000:081.735 - 0.054ms returns 682060510
T17578 000:086.288 JLINK_GetOEMString(...)
T17578 000:096.973 JLINK_TIF_Select(JLINKARM_TIF_SWD)
T17578 000:097.628 - 0.671ms returns 0x00
T17578 000:097.653 JLINK_HasError()
T17578 000:099.547 JLINK_SetSpeed(5000)
T17578 000:099.820 - 0.282ms
T17578 000:099.835 JLINK_GetId()
T17578 000:105.067 InitTarget() start
T17578 000:105.093 J-Link Script File: Executing InitTarget()
T17578 000:108.737 Looking for J-Link GUI Server exe at: C:\Keil_v5\ARM\Segger\JLinkGUIServer.exe
T17578 000:108.890 Looking for J-Link GUI Server exe at: C:\Program Files\SEGGER\JLink_V818\JLinkGUIServer.exe
T17578 000:108.954 Forking J-Link GUI Server: C:\Program Files\SEGGER\JLink_V818\JLinkGUIServer.exe
T17578 000:181.575 J-Link GUI Server info: "J-Link GUI server V8.18 "
T17578 002:406.198 Device will be unsecured now.
T17578 002:631.975 InitTarget() end
T17578 002:796.797 InitTarget() start
T17578 002:796.830 J-Link Script File: Executing InitTarget()
T17578 002:911.808 InitTarget() end
T17578 003:014.808 - 2915.023ms returns 0x00000000
T17578 006:160.609 JLINK_Close()
T17578 006:185.982 - 25.395ms
T17578 006:186.008
T17578 006:186.012 Closed
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/JLinkSettings.ini
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[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
RMWThreshold = 0x400
Loaders=""
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF
[RAM]
VerifyDownload = 0x00
[DYN_MEM_MAP]
NumUserRegion = 0x00
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/RTE/Device/nRF52840_xxAA/arm_startup_nrf52840.s
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; Copyright (c) 2009-2021 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
; Licensed under the Apache License, Version 2.0 (the License); you may
; not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an AS IS BASIS, WITHOUT
; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
; NOTICE: This file has been modified by Nordic Semiconductor ASA.
IF :DEF: __STARTUP_CONFIG
#ifdef __STARTUP_CONFIG
#include "startup_config.h"
#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
#endif
#endif
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 16384
ENDIF
IF :DEF: __STARTUP_CONFIG
Stack_Align EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
ELSE
Stack_Align EQU 3
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=Stack_Align
Stack_Mem SPACE Stack_Size
__initial_sp
IF :DEF: __STARTUP_CONFIG
Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 16384
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0 ; Reserved
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD NFCT_IRQHandler
DCD GPIOTE_IRQHandler
DCD SAADC_IRQHandler
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
DCD RTC0_IRQHandler
DCD TEMP_IRQHandler
DCD RNG_IRQHandler
DCD ECB_IRQHandler
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
DCD QDEC_IRQHandler
DCD COMP_LPCOMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
DCD SWI2_EGU2_IRQHandler
DCD SWI3_EGU3_IRQHandler
DCD SWI4_EGU4_IRQHandler
DCD SWI5_EGU5_IRQHandler
DCD TIMER3_IRQHandler
DCD TIMER4_IRQHandler
DCD PWM0_IRQHandler
DCD PDM_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD MWU_IRQHandler
DCD PWM1_IRQHandler
DCD PWM2_IRQHandler
DCD SPIM2_SPIS2_SPI2_IRQHandler
DCD RTC2_IRQHandler
DCD I2S_IRQHandler
DCD FPU_IRQHandler
DCD USBD_IRQHandler
DCD UARTE1_IRQHandler
DCD QSPI_IRQHandler
DCD CRYPTOCELL_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PWM3_IRQHandler
DCD 0 ; Reserved
DCD SPIM3_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemoryManagement_Handler\
PROC
EXPORT MemoryManagement_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler [WEAK]
EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
EXPORT NFCT_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
EXPORT SAADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT RTC0_IRQHandler [WEAK]
EXPORT TEMP_IRQHandler [WEAK]
EXPORT RNG_IRQHandler [WEAK]
EXPORT ECB_IRQHandler [WEAK]
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
EXPORT QDEC_IRQHandler [WEAK]
EXPORT COMP_LPCOMP_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
EXPORT SWI2_EGU2_IRQHandler [WEAK]
EXPORT SWI3_EGU3_IRQHandler [WEAK]
EXPORT SWI4_EGU4_IRQHandler [WEAK]
EXPORT SWI5_EGU5_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT TIMER4_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PDM_IRQHandler [WEAK]
EXPORT MWU_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
EXPORT RTC2_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
EXPORT USBD_IRQHandler [WEAK]
EXPORT UARTE1_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT CRYPTOCELL_IRQHandler [WEAK]
EXPORT PWM3_IRQHandler [WEAK]
EXPORT SPIM3_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
NFCT_IRQHandler
GPIOTE_IRQHandler
SAADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
RTC0_IRQHandler
TEMP_IRQHandler
RNG_IRQHandler
ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
QDEC_IRQHandler
COMP_LPCOMP_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
SWI2_EGU2_IRQHandler
SWI3_EGU3_IRQHandler
SWI4_EGU4_IRQHandler
SWI5_EGU5_IRQHandler
TIMER3_IRQHandler
TIMER4_IRQHandler
PWM0_IRQHandler
PDM_IRQHandler
MWU_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
SPIM2_SPIS2_SPI2_IRQHandler
RTC2_IRQHandler
I2S_IRQHandler
FPU_IRQHandler
USBD_IRQHandler
UARTE1_IRQHandler
QSPI_IRQHandler
CRYPTOCELL_IRQHandler
PWM3_IRQHandler
SPIM3_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/RTE/Device/nRF52840_xxAA/system_nrf52.c
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/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "nrf_peripherals.h"
#include "nrf52_erratas.h"
#include "system_nrf52.h"
#include "system_nrf52_approtect.h"
#define __SYSTEM_CLOCK_64M (64000000UL)
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#endif
/* Select correct reset pin */
/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */
#if defined (DEVELOP_IN_NRF52805) \
|| defined (DEVELOP_IN_NRF52810) \
|| defined (DEVELOP_IN_NRF52811) \
|| defined (DEVELOP_IN_NRF52832)
#define RESET_PIN 21
#elif defined (DEVELOP_IN_NRF52820) \
|| defined (DEVELOP_IN_NRF52833) \
|| defined (DEVELOP_IN_NRF52840)
#define RESET_PIN 18
#elif defined (NRF52805_XXAA) \
|| defined (NRF52810_XXAA) \
|| defined (NRF52811_XXAA) \
|| defined (NRF52832_XXAA) \
|| defined (NRF52832_XXAB)
#define RESET_PIN 21
#elif defined (NRF52820_XXAA) \
|| defined (NRF52833_XXAA) \
|| defined (NRF52840_XXAA)
#define RESET_PIN 18
#else
#error "A supported device macro must be defined."
#endif
/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
}
/* Configure the NVMC to "mode".
Mode must be an enumerator of field NVMC_CONFIG_WEN */
void nvmc_config(uint32_t mode)
{
NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
nvmc_wait();
}
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK_64M;
}
void SystemInit(void)
{
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#if NRF52_ERRATA_12_ENABLE_WORKAROUND
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_12()){
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
}
#endif
#if NRF52_ERRATA_16_ENABLE_WORKAROUND
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_16()){
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
}
#endif
#if NRF52_ERRATA_31_ENABLE_WORKAROUND
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
#endif
#if NRF52_ERRATA_32_ENABLE_WORKAROUND
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
#endif
#if NRF52_ERRATA_36_ENABLE_WORKAROUND
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
}
#endif
#if NRF52_ERRATA_37_ENABLE_WORKAROUND
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
#endif
#if NRF52_ERRATA_57_ENABLE_WORKAROUND
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_57()){
*(volatile uint32_t *)0x40005610 = 0x00000005;
*(volatile uint32_t *)0x40005688 = 0x00000001;
*(volatile uint32_t *)0x40005618 = 0x00000000;
*(volatile uint32_t *)0x40005614 = 0x0000003F;
}
#endif
#if NRF52_ERRATA_66_ENABLE_WORKAROUND
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
}
#endif
#if NRF52_ERRATA_98_ENABLE_WORKAROUND
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_98()){
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
}
#endif
#if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
#endif
#if NRF52_ERRATA_108_ENABLE_WORKAROUND
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_108()){
*(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
}
#endif
#if NRF52_ERRATA_115_ENABLE_WORKAROUND
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_115()){
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
}
#endif
#if NRF52_ERRATA_120_ENABLE_WORKAROUND
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_120()){
*(volatile uint32_t *)0x40029640ul = 0x200ul;
}
#endif
#if NRF52_ERRATA_136_ENABLE_WORKAROUND
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
#endif
#if NRF52_ERRATA_182_ENABLE_WORKAROUND
/* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_182()){
*(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
}
#endif
#if NRF52_ERRATA_217_ENABLE_WORKAROUND
/* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_217()){
*(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful;
}
#endif
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
nrf52_handle_approtect();
#if NRF52_CONFIGURATION_249_ENABLE && (defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || defined(NRF52811_XXAA))
if (nrf52_configuration_249() && (NRF_UICR->NRFMDK[0] == 0xFFFFFFFF || NRF_UICR->NRFMDK[1] == 0xFFFFFFFF))
{
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NRFMDK[0] = 0;
nvmc_wait();
NRF_UICR->NRFMDK[1] = 0;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
}
#endif
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS) && defined(NFCT_PRESENT)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->PSELRESET[0] = RESET_PIN;
nvmc_wait();
NRF_UICR->PSELRESET[1] = RESET_PIN;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* When developing for nRF52810 on an nRF52832, or nRF52811 on an nRF52840,
make sure NFC pins are mapped as GPIO. */
#if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \
|| defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA)
if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){
nvmc_config(NVMC_CONFIG_WEN_Wen);
*((uint32_t *)0x1000120C) = 0;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
SystemCoreClockUpdate();
}
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/RTE/Device/nRF52840_xxAA/system_nrf52.c.base@8.44.1
+329
View File
@@ -0,0 +1,329 @@
/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "nrf_peripherals.h"
#include "nrf52_erratas.h"
#include "system_nrf52.h"
#include "system_nrf52_approtect.h"
#define __SYSTEM_CLOCK_64M (64000000UL)
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#endif
/* Select correct reset pin */
/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */
#if defined (DEVELOP_IN_NRF52805) \
|| defined (DEVELOP_IN_NRF52810) \
|| defined (DEVELOP_IN_NRF52811) \
|| defined (DEVELOP_IN_NRF52832)
#define RESET_PIN 21
#elif defined (DEVELOP_IN_NRF52820) \
|| defined (DEVELOP_IN_NRF52833) \
|| defined (DEVELOP_IN_NRF52840)
#define RESET_PIN 18
#elif defined (NRF52805_XXAA) \
|| defined (NRF52810_XXAA) \
|| defined (NRF52811_XXAA) \
|| defined (NRF52832_XXAA) \
|| defined (NRF52832_XXAB)
#define RESET_PIN 21
#elif defined (NRF52820_XXAA) \
|| defined (NRF52833_XXAA) \
|| defined (NRF52840_XXAA)
#define RESET_PIN 18
#else
#error "A supported device macro must be defined."
#endif
/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
}
/* Configure the NVMC to "mode".
Mode must be an enumerator of field NVMC_CONFIG_WEN */
void nvmc_config(uint32_t mode)
{
NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
nvmc_wait();
}
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK_64M;
}
void SystemInit(void)
{
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#if NRF52_ERRATA_12_ENABLE_WORKAROUND
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_12()){
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
}
#endif
#if NRF52_ERRATA_16_ENABLE_WORKAROUND
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_16()){
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
}
#endif
#if NRF52_ERRATA_31_ENABLE_WORKAROUND
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
#endif
#if NRF52_ERRATA_32_ENABLE_WORKAROUND
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
#endif
#if NRF52_ERRATA_36_ENABLE_WORKAROUND
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
}
#endif
#if NRF52_ERRATA_37_ENABLE_WORKAROUND
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
#endif
#if NRF52_ERRATA_57_ENABLE_WORKAROUND
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_57()){
*(volatile uint32_t *)0x40005610 = 0x00000005;
*(volatile uint32_t *)0x40005688 = 0x00000001;
*(volatile uint32_t *)0x40005618 = 0x00000000;
*(volatile uint32_t *)0x40005614 = 0x0000003F;
}
#endif
#if NRF52_ERRATA_66_ENABLE_WORKAROUND
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
}
#endif
#if NRF52_ERRATA_98_ENABLE_WORKAROUND
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_98()){
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
}
#endif
#if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
#endif
#if NRF52_ERRATA_108_ENABLE_WORKAROUND
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_108()){
*(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
}
#endif
#if NRF52_ERRATA_115_ENABLE_WORKAROUND
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_115()){
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
}
#endif
#if NRF52_ERRATA_120_ENABLE_WORKAROUND
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_120()){
*(volatile uint32_t *)0x40029640ul = 0x200ul;
}
#endif
#if NRF52_ERRATA_136_ENABLE_WORKAROUND
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
#endif
#if NRF52_ERRATA_182_ENABLE_WORKAROUND
/* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_182()){
*(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
}
#endif
#if NRF52_ERRATA_217_ENABLE_WORKAROUND
/* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_217()){
*(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful;
}
#endif
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
nrf52_handle_approtect();
#if NRF52_CONFIGURATION_249_ENABLE && (defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || defined(NRF52811_XXAA))
if (nrf52_configuration_249() && (NRF_UICR->NRFMDK[0] == 0xFFFFFFFF || NRF_UICR->NRFMDK[1] == 0xFFFFFFFF))
{
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NRFMDK[0] = 0;
nvmc_wait();
NRF_UICR->NRFMDK[1] = 0;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
}
#endif
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS) && defined(NFCT_PRESENT)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->PSELRESET[0] = RESET_PIN;
nvmc_wait();
NRF_UICR->PSELRESET[1] = RESET_PIN;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* When developing for nRF52810 on an nRF52832, or nRF52811 on an nRF52840,
make sure NFC pins are mapped as GPIO. */
#if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \
|| defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA)
if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){
nvmc_config(NVMC_CONFIG_WEN_Wen);
*((uint32_t *)0x1000120C) = 0;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
SystemCoreClockUpdate();
}
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/RTE/Device/nRF52840_xxAA/system_nrf52.c.update@8.40.3
+317
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@@ -0,0 +1,317 @@
/*
Copyright (c) 2009-2021 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
Licensed under the Apache License, Version 2.0 (the License); you may
not use this file except in compliance with the License.
You may obtain a copy of the License at
www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
NOTICE: This file has been modified by Nordic Semiconductor ASA.
*/
/* NOTE: Template files (including this one) are application specific and therefore expected to
be copied into the application project folder prior to its use! */
#include <stdint.h>
#include <stdbool.h>
#include "nrf.h"
#include "nrf_peripherals.h"
#include "nrf_erratas.h"
#include "system_nrf52.h"
#include "system_nrf52_approtect.h"
#define __SYSTEM_CLOCK_64M (64000000UL)
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#elif defined ( __ICCARM__ )
__root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
#endif
/* Select correct reset pin */
/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */
#if defined (DEVELOP_IN_NRF52805) \
|| defined (DEVELOP_IN_NRF52810) \
|| defined (DEVELOP_IN_NRF52811) \
|| defined (DEVELOP_IN_NRF52832)
#define RESET_PIN 21
#elif defined (DEVELOP_IN_NRF52820) \
|| defined (DEVELOP_IN_NRF52833) \
|| defined (DEVELOP_IN_NRF52840)
#define RESET_PIN 18
#elif defined (NRF52805_XXAA) \
|| defined (NRF52810_XXAA) \
|| defined (NRF52811_XXAA) \
|| defined (NRF52832_XXAA) \
|| defined (NRF52832_XXAB)
#define RESET_PIN 21
#elif defined (NRF52820_XXAA) \
|| defined (NRF52833_XXAA) \
|| defined (NRF52840_XXAA)
#define RESET_PIN 18
#else
#error "A supported device macro must be defined."
#endif
/* -- NVMC utility functions -- */
/* Waits until NVMC is done with the current pending action */
void nvmc_wait(void)
{
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
}
/* Configure the NVMC to "mode".
Mode must be an enumerator of field NVMC_CONFIG_WEN */
void nvmc_config(uint32_t mode)
{
NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos;
nvmc_wait();
}
void SystemCoreClockUpdate(void)
{
SystemCoreClock = __SYSTEM_CLOCK_64M;
}
void SystemInit(void)
{
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
Specification to see which one). */
#if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
Specification to see which ones). */
#if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos)
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
#endif
#if NRF52_ERRATA_12_ENABLE_WORKAROUND
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_12()){
*(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8;
}
#endif
#if NRF52_ERRATA_16_ENABLE_WORKAROUND
/* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_16()){
*(volatile uint32_t *)0x4007C074 = 3131961357ul;
}
#endif
#if NRF52_ERRATA_31_ENABLE_WORKAROUND
/* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_31()){
*(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
}
#endif
#if NRF52_ERRATA_32_ENABLE_WORKAROUND
/* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_32()){
CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
}
#endif
#if NRF52_ERRATA_36_ENABLE_WORKAROUND
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_36()){
NRF_CLOCK->EVENTS_DONE = 0;
NRF_CLOCK->EVENTS_CTTO = 0;
NRF_CLOCK->CTIV = 0;
}
#endif
#if NRF52_ERRATA_37_ENABLE_WORKAROUND
/* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_37()){
*(volatile uint32_t *)0x400005A0 = 0x3;
}
#endif
#if NRF52_ERRATA_57_ENABLE_WORKAROUND
/* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_57()){
*(volatile uint32_t *)0x40005610 = 0x00000005;
*(volatile uint32_t *)0x40005688 = 0x00000001;
*(volatile uint32_t *)0x40005618 = 0x00000000;
*(volatile uint32_t *)0x40005614 = 0x0000003F;
}
#endif
#if NRF52_ERRATA_66_ENABLE_WORKAROUND
/* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_66()){
NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
}
#endif
#if NRF52_ERRATA_98_ENABLE_WORKAROUND
/* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_98()){
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
}
#endif
#if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos)
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_103()){
NRF_CCM->MAXPACKETSIZE = 0xFBul;
}
#endif
#if NRF52_ERRATA_108_ENABLE_WORKAROUND
/* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_108()){
*(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful;
}
#endif
#if NRF52_ERRATA_115_ENABLE_WORKAROUND
/* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_115()){
*(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F);
}
#endif
#if NRF52_ERRATA_120_ENABLE_WORKAROUND
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_120()){
*(volatile uint32_t *)0x40029640ul = 0x200ul;
}
#endif
#if NRF52_ERRATA_136_ENABLE_WORKAROUND
/* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_136()){
if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){
NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk;
}
}
#endif
#if NRF52_ERRATA_182_ENABLE_WORKAROUND
/* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_182()){
*(volatile uint32_t *) 0x4000173C |= (0x1 << 10);
}
#endif
#if NRF52_ERRATA_217_ENABLE_WORKAROUND
/* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document
for your device located at https://infocenter.nordicsemi.com/index.jsp */
if (nrf52_errata_217()){
*(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful;
}
#endif
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
* operations are not used in your code. */
#if (__FPU_USED == 1)
SCB->CPACR |= (3UL << 20) | (3UL << 22);
__DSB();
__ISB();
#endif
nrf52_handle_approtect();
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
normal GPIOs. */
#if defined (CONFIG_NFCT_PINS_AS_GPIOS) && defined(NFCT_PRESENT)
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
reserved for PinReset and not available as normal GPIO. */
#if defined (CONFIG_GPIO_AS_PINRESET)
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
nvmc_config(NVMC_CONFIG_WEN_Wen);
NRF_UICR->PSELRESET[0] = RESET_PIN;
nvmc_wait();
NRF_UICR->PSELRESET[1] = RESET_PIN;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
/* When developing for nRF52810 on an nRF52832, or nRF52811 on an nRF52840,
make sure NFC pins are mapped as GPIO. */
#if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \
|| defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA)
if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){
nvmc_config(NVMC_CONFIG_WEN_Wen);
*((uint32_t *)0x1000120C) = 0;
nvmc_wait();
nvmc_config(NVMC_CONFIG_WEN_Ren);
NVIC_SystemReset();
}
#endif
SystemCoreClockUpdate();
}
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/RTE/_flash_s140_nrf52_7.2.0_softdevice/RTE_Components.h
+21
View File
@@ -0,0 +1,21 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'ble_app_bladder_patch_s140'
* Target: 'flash_s140_nrf52_7.2.0_softdevice'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "nrf.h"
#endif /* RTE_COMPONENTS_H */
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/RTE/_nrf52840_xxaa/RTE_Components.h
+21
View File
@@ -0,0 +1,21 @@
/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'ble_app_bladder_patch_s140'
* Target: 'nrf52840_xxaa'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "nrf.h"
#endif /* RTE_COMPONENTS_H */
project/ble_peripheral/ble_app_bladder_patch/pca10056/s140/arm5_no_packs/_nrf52840_xxaa.BAT
+173
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@@ -0,0 +1,173 @@
SET PATH=C:\Keil_v5\ARM\ARMCC\Bin;C:\Program Files\Common Files\Oracle\Java\javapath;C:\Program Files (x86)\Common Files\Oracle\Java\java8path;C:\Program Files (x86)\Common Files\Oracle\Java\javapath;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\WINDOWS\System32\OpenSSH\;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\Program Files\dotnet\;C:\Program Files (x86)\Windows Kits\10\Windows Performance Toolkit\;D:\go\bin;C:\Program Files\Git\cmd;d:\nrfutil\bin;D:\nrfutil\bin\;C:\Program Files\eProsima\fastdds 3.2.2\bin;C:\Program Files\eProsima\fastdds 3.2.2\bin\x64Win64VS2019;C:\Users\CharlesKWON\AppData\Local\Microsoft\WindowsApps;C:\Users\CharlesKWON\AppData\Local\Programs\Microsoft VS Code\bin;C:\Users\CharlesKWON\.dotnet\tools;C:\Users\CharlesKWON\go\bin;C:\Users\CharlesKWON\AppData\Local\PowerToys\
SET CPU_TYPE=nRF52840_xxAA
SET CPU_VENDOR=Nordic Semiconductor
SET UV2_TARGET=nrf52840_xxaa
SET CPU_CLOCK=0x03D09000
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\main.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\main_timer.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ada2200_spi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ad5272_i2c.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\battery_saadc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\mcp4725_i2c.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\power_control.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\tmp235_q1.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\measurements.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\fstorage.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\mcp4725_adc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\meas_pd_voltage_simple.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\full_agc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ir_i2c.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\led_parse.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cat_interface.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cmd_parse.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\meas_pd_imm.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\meas_pd_48.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\pulse_gen.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\i2c_manager.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\parser.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_quick_security.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\dr_piezo.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\dr_util.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\dr_adc121s051.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\boards.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\bsp.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\bsp_btn_ble.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\utf.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_advdata.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_advertising.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_conn_params.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_conn_state.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_link_ctx_manager.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_srv_common.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_ble_gatt.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_ble_qwr.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\peer_manager.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\peer_manager_handler.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\pm_buffer.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\peer_data_storage.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\peer_database.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\peer_id.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\security_dispatcher.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\security_manager.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\gatt_cache_manager.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\id_manager.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\gatts_cache_manager.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_ble_lesc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_nus.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_drv_clock.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_drv_uart.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_atomic.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_clock.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_gpiote.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_prs.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_uart.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_uarte.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_twi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_saadc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_timer.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_ppi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_drv_ppi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_drv_spi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_spi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_spim.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_drv_twi.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_twim.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrfx_pwm.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_button.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_error.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_error_handler_keil.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_error_weak.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_fifo.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_scheduler.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_timer2.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_uart_fifo.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_util_platform.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\drv_rtc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\hardfault_implementation.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_assert.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_atfifo.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_atflags.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_atomic.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_balloc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_fprintf.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_fprintf_format.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_memobj.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_pwr_mgmt.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_ringbuf.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_section_iter.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_sortlist.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_strerror.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\retarget.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\crc16.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_fstorage.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_fstorage_sd.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\fds.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_log_backend_rtt.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_log_backend_serial.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_log_default_backends.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_log_frontend.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_log_str_formatter.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\segger_rtt.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\segger_rtt_syscalls_keil.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\segger_rtt_printf.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_sdh.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_sdh_ble.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_sdh_soc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_dfu.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_dfu_bonded.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ble_dfu_unbonded.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_dfu_svci.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_aead.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_aes.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_aes_shared.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_ecc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_ecdh.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_ecdsa.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_eddsa.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_error.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_hash.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_hkdf.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_hmac.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_init.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_rng.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_crypto_shared.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_aes.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_aes_aead.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_chacha_poly_aead.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_ecc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_ecdh.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_ecdsa.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_eddsa.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_hash.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_hmac.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_init.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_mutex.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_rng.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\cc310_backend_shared.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\oberon_backend_chacha_poly_aead.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\oberon_backend_ecc.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\oberon_backend_ecdh.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\oberon_backend_ecdsa.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\oberon_backend_eddsa.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\oberon_backend_hash.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\oberon_backend_hmac.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_hw_backend_init.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_hw_backend_rng.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\nrf_hw_backend_rng_mbedtls.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\aes.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\ctr_drbg.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\platform_util.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\system_interface.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\dataconverter.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\errorhelper.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\invbasicmath.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\inv_imu_apex.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\inv_imu_driver.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\inv_imu_selftest.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\inv_imu_transport.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_raw.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\app_raw_main.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmAsm" --Via ".\_build\arm_startup_nrf52840._ia"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmCC" --Via ".\_build\system_nrf52.__i"
"C:\Keil_v5\ARM\ARMCC\Bin\ArmLink" --Via ".\_build\nrf52840_xxaa.lnp"
"C:\Keil_v5\ARM\ARMCC\Bin\fromelf.exe" ".\_build\nrf52840_xxaa.axf" --i32combined --output ".\_build\nrf52840_xxaa.hex"
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/*******************************************************************************
* @file i2c_manager.h
* @brief Common header for HW/SW I2C mutex control
******************************************************************************/
#ifndef __I2C_MANAGER_H__
#define __I2C_MANAGER_H__
#include <stdbool.h>
#include "app_error.h"
extern bool HW_I2C_FRQ;
extern bool SW_I2C_FRQ;
void hw_i2c_init_once(void);
void sw_i2c_init_once(void);
void i2c_reset_state(void);
#endif
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/*******************************************************************************
* @file i2c_manager.c
* @brief Robust HW/SW I2C switching logic with mutual exclusion
******************************************************************************/
#include "i2c_manager.h"
#include "debug_print.h"
#include "nrf_delay.h"
#include "eeprom_driver.h"
#include "mcp4725_i2c.h"
#include "nrf_drv_twi.h"
#include "cat_interface.h"
bool HW_I2C_FRQ = false;
bool SW_I2C_FRQ = false;
extern const nrf_drv_twi_t m_eeprom;
/* -------------------------------------------------------------------------- */
/* HW (TWI) 초기화 */
/* -------------------------------------------------------------------------- */
void hw_i2c_init_once(void)
{
if (SW_I2C_FRQ)
{
DBG_PRINTF("[I2C] SW I2C active - forcing HW switch\r\n");
// SW 비활성화 후 전환
SW_I2C_FRQ = false;
}
if (HW_I2C_FRQ)
{
DBG_PRINTF("[I2C] HW I2C already initialized\r\n");
return;
}
DBG_PRINTF("[I2C] Initializing HW (TWI) I2C...\r\n");
eeprom_initialize();
nrf_delay_ms(2);
HW_I2C_FRQ = true;
SW_I2C_FRQ = false;
DBG_PRINTF("[I2C] HW I2C initialized\r\n");
}
/* -------------------------------------------------------------------------- */
/* SW (Port-Bang) 초기화 */
/* -------------------------------------------------------------------------- */
void sw_i2c_init_once(void)
{
if (HW_I2C_FRQ)
{
DBG_PRINTF("[I2C] HW I2C active -> switching to SW I2C\r\n");
// HW 완전 종료
nrf_drv_twi_disable(&m_eeprom);
nrf_drv_twi_uninit(&m_eeprom);
nrf_delay_ms(3);
HW_I2C_FRQ = false; // 반드시 false로 갱신
}
// HW 모드가 종료되었으니 SW 시작 가능
if (!SW_I2C_FRQ)
{
DBG_PRINTF("[I2C] Initializing SW (Port Bang-Bang) I2C...\r\n");
eeprom_uninitialize(); // SDA/SCL 해제
nrf_delay_ms(1);
mcp4725_init(); // 소프트 I2C 초기화
SW_I2C_FRQ = true;
HW_I2C_FRQ = false;
DBG_PRINTF("[I2C] SW I2C initialized\r\n");
}
else
{
DBG_PRINTF("[I2C] SW I2C already active\r\n");
}
}
/* -------------------------------------------------------------------------- */
/* RESET STATE */
/* -------------------------------------------------------------------------- */
void i2c_reset_state(void)
{
HW_I2C_FRQ = false;
SW_I2C_FRQ = false;
DBG_PRINTF("[I2C] Flags reset\r\n");
}